Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9799747 | Low resistance contact for semiconductor devices | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-10-24 |
| 9786756 | Self-aligned source and drain regions for semiconductor devices | Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2017-10-10 |
| 9768254 | Leakage-free implantation-free ETSOI transistors | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana | 2017-09-19 |
| 9673290 | Self-aligned source and drain regions for semiconductor devices | Bahman Hekmatshoartabari, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2017-06-06 |
| 9653570 | Junction interlayer dielectric for reducing leakage current in semiconductor devices | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-05-16 |
| 9620592 | Doped zinc oxide and n-doping to reduce junction leakage | Keith E. Fogel, Jeehwan Kim, Siegfried Maurer, Devendra K. Sadana | 2017-04-11 |
| 9601624 | SOI based FINFET with strained source-drain regions | Stephen W. Bedell, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Dominic J. Schepis | 2017-03-21 |
| 9590077 | Local SOI fins with multiple heights | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2017-03-07 |
| 9583562 | Reduction of defect induced leakage in III-V semiconductor devices | Jeehwan Kim, Devendra K. Sadana, Brent A. Wacaser | 2017-02-28 |
| 9553056 | Semiconductor chip having tampering feature | Ali Afzali-Ardakani, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana | 2017-01-24 |
| 9536945 | MOSFET with ultra low drain leakage | Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana | 2017-01-03 |