SJ

Syun-Ming Jang

TSMC: 334 patents #31 of 12,232Top 1%
Overall (All Time): #977 of 4,157,543Top 1%
337
Patents All Time

Issued Patents All Time

Showing 201–225 of 337 patents

Patent #TitleCo-InventorsDate
6391792 Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer Juing-Yi Cheng, Chung-Long Chang 2002-05-21
6387775 Fabrication of MIM capacitor in copper damascene process Mong-Song Liang 2002-05-14
6383930 Method to eliminate copper CMP residue of an alignment mark for damascene processes Ying-Ho Chen, Wen-Chih Chiou, Tsu Shih 2002-05-07
6376377 Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity Weng Chang, Ying-Ho Chen, Jih-Churng Twu 2002-04-23
6372664 Crack resistant multi-layer dielectric layer and method for formation thereof Chu-Yun Fu, Chen-Hua Yu 2002-04-16
6368952 Diffusion inhibited dielectric structure for diffusion enhanced conductor layer Mong-Song Liang 2002-04-09
6365523 Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layers Chu-Yun Fu, Ying-Ho Chen 2002-04-02
6362085 Method for reducing gate oxide effective thickness and leakage current Mo Yu, Chen-Hua Yu 2002-03-26
6362093 Dual damascene method employing sacrificial via fill layer Anthony Yen, Hung-Chang Hsieh 2002-03-26
6358119 Way to remove CU line damage after CU CMP Tsu Shih, Jih-Churng Twu, Ying-Ho Chen 2002-03-19
6358841 Method of copper CMP on low dielectric constant HSQ material Tien-I Bao 2002-03-19
6358839 Solution to black diamond film delamination problem Lain-Jong Li, Shwangming Jeng 2002-03-19
6350364 Method for improvement of planarity of electroplated copper 2002-02-26
6350693 Method of CMP of polysilicon Chung-Long Chang 2002-02-26
6350694 Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials Weng Chang, Tien-I Bao 2002-02-26
6346476 Method for enhancing line-to-line capacitance uniformity of plasma enhanced chemical vapor deposited (PECVD) inter-metal dielectric (IMD) layers Weng Chang 2002-02-12
6329717 Integrated circuit having selectivity deposited silicon oxide spacer layer formed therein Chen-Hua Yu, Lung Chen, Lin-June Wu 2001-12-11
6319809 Method to reduce via poison in low-k Cu dual damascene by UV-treatment Weng Chang, Lain-Jong Li, Shwang-Ming Jeng 2001-11-20
6319784 Using high temperature H2 anneal to recrystallize S/D and remove native oxide simultaneously Mo Yu 2001-11-20
6316348 High selectivity Si-rich SiON etch-stop layer Chu-Yun Fu, Chia-Shiung Tsai 2001-11-13
6297162 Method to reduce silicon oxynitride etch rate in a silicon oxide dry etch Chu-Yan Fu, Yuan-Hung Chiu 2001-10-02
6277745 Passivation method of post copper dry etching Chung-Shi Liu, Shau-Lin Shue, Chen-Hua Yu 2001-08-21
6274483 Method to improve metal line adhesion by trench corner shape modification Weng Chang, Ying-Ho Chen 2001-08-14
6274514 HDP-CVD method for forming passivation layers with enhanced adhesion Chu-Yun Fu 2001-08-14
6271138 Chemical mechanical polish (CMP) planarizing method with enhanced chemical mechanical polish (CMP) planarized layer planarity Weng Chang 2001-08-07