Issued Patents All Time
Showing 251–275 of 337 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6194307 | Elimination of copper line damages for damascene process | Ying-Ho Chen | 2001-02-27 |
| 6194287 | Shallow trench isolation (STI) method with reproducible alignment registration | — | 2001-02-27 |
| 6191039 | Method of CMP of polysilicon | Chung-Long Chang | 2001-02-20 |
| 6187663 | Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials | Chen-Hua Yu, Weng Chang, Yao-Yi Cheng | 2001-02-13 |
| 6184155 | Method for forming a ultra-thin gate insulator layer | Mo Yu, Mong-Song Liang | 2001-02-06 |
| 6181013 | Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby | Chung-Shi Liu, Chen-Hua Yu, Tien-I Bao | 2001-01-30 |
| 6180540 | Method for forming a stabilized fluorosilicate glass layer | — | 2001-01-30 |
| 6180543 | Method of generating two nitrogen concentration peak profiles in gate oxide | Mo Yu | 2001-01-30 |
| 6176141 | Method for stud pull test for film formed on semiconductor device | Lung-Hsiang Chuang, Chung-Long Chang, Ying-Chen Chao | 2001-01-23 |
| 6174800 | Via formation in a poly(arylene ether) inter metal dielectric layer | — | 2001-01-16 |
| 6174797 | Silicon oxide dielectric material with excess silicon as diffusion barrier layer | Tien-I Bao | 2001-01-16 |
| 6174808 | Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS | Chu-Yun Fu | 2001-01-16 |
| 6171896 | Method of forming shallow trench isolation by HDPCVD oxide | Chen-Hua Yu, Ying-Ho Chen | 2001-01-09 |
| 6165915 | Forming halogen doped glass dielectric layer with enhanced stability | — | 2000-12-26 |
| 6165898 | Dual damascene patterned conductor layer formation method without etch stop layer | Chen-Hua Yu | 2000-12-26 |
| 6165897 | Void forming method for fabricating low dielectric constant dielectric layer | — | 2000-12-26 |
| 6165052 | Method and apparatus for chemical/mechanical planarization (CMP) of a semiconductor substrate having shallow trench isolation | Chen-Hua Yu | 2000-12-26 |
| 6153512 | Process to improve adhesion of HSQ to underlying materials | Chung-Long Chang | 2000-11-28 |
| 6143673 | Method for forming gap filling silicon oxide intermetal dielectric (IMD) layer formed employing ozone-tEOS | Ying-Ho Chen, Shwangming Jeng, Chen-Hua Yu | 2000-11-07 |
| 6143670 | Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer | Yao-Yi Cheng, Chia-Shiung Tsai, Chung-Shi Liu | 2000-11-07 |
| 6136680 | Methods to improve copper-fluorinated silica glass interconnects | Jane-Bai Lai, Chung-Shi Liu, Tien-I Bao, Chung-Long Chang, Hui Wang +4 more | 2000-10-24 |
| 6136679 | Gate micro-patterning process | Chen-Hwa Yu | 2000-10-24 |
| 6121111 | Method of removing tungsten near the wafer edge after CMP | Chen-Hua Yu, Shwangming Jeng | 2000-09-19 |
| 6114253 | Via patterning for poly(arylene ether) used as an inter-metal dielectric | Ming-Hsin Huang, Chen-Hua Yu | 2000-09-05 |
| 6110648 | Method of enclosing copper conductor in a dual damascene process | — | 2000-08-29 |