Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6329717 | Integrated circuit having selectivity deposited silicon oxide spacer layer formed therein | Syun-Ming Jang, Chen-Hua Yu, Lin-June Wu | 2001-12-11 |
| 6040227 | IPO deposited with low pressure O.sub.3 -TEOS for planarization in multi-poly memory technology | Shou-Gwo Wuu, Dun-Nian Yaung, Yi-Miaw Lin | 2000-03-21 |
| 5904573 | PE-TEOS process | Syun-Ming Jang, Chen-Hua Yu | 1999-05-18 |
| 5631197 | Sacrificial etchback layer for improved spin-on-glass planarization | Chen-Hua Yu, Syun-Ming Jang, Yuan-Chang Huang | 1997-05-20 |
| 5518959 | Method for selectively depositing silicon oxide spacer layers | Syun-Ming Jang, Chen-Hua Yu, Lin-June Wu | 1996-05-21 |