Issued Patents All Time
Showing 76–100 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6911369 | Discontinuity prevention for SiGe deposition | Kuen-Chyr Lee, Liang-Gi Yao, Fu Chin Yang, Shih-Chang Chen | 2005-06-28 |
| 6900269 | Halogen-free resin composition | Kuen-Yuan Hwang, An-Pang Tu, Chi-Yi Ju, Sheng Yen Wu, Chun-Hsiung Kao +1 more | 2005-05-31 |
| 6878610 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2005-04-12 |
| 6806192 | Method of barrier-less integration with copper alloy | Jing-Cheng Lin, Cheng-Lin Huang, Ching-Hua Hsieh, Shau-Lin Shue | 2004-10-19 |
| 6793797 | Method for integrating an electrodeposition and electro-mechanical polishing process | Shih-Wei Chou, Ming-Hsing Tsai, Winston Shue | 2004-09-21 |
| 6767847 | Method of forming a silicon nitride-silicon dioxide gate stack | Chien-Ming Hu, Chien-Hao Chen, Mo Yu, Shih-Chang Chen | 2004-07-27 |
| 6753259 | Method of improving the bondability between Au wires and Cu bonding pads | Syun-Ming Jang, Chen-Hua Yu, Chung-Shi Liu, Jane-Bai Lai | 2004-06-22 |
| 6740567 | Laminating method for forming integrated circuit microelectronic fabrication | Syun-Ming Jang | 2004-05-25 |
| 6716753 | Method for forming a self-passivated copper interconnect structure | Shau-Lin Shue | 2004-04-06 |
| 6706629 | Barrier-free copper interconnect | Jing-Cheng Lin, Cheng-Lin Huang, Winston Shue | 2004-03-16 |
| 6649513 | Copper back-end-of-line by electropolish | Ming-Hsing Tsai, Shih-Wei Chou, Winston Shue | 2003-11-18 |
| 6600186 | Process technology architecture of embedded DRAM | Jin-Yuan Lee | 2003-07-29 |
| 6590344 | Selectively controllable gas feed zones for a plasma reactor | Shun-Jan Tao, Huan-Just Lin | 2003-07-08 |
| 6566703 | High speed flash memory with high coupling ratio | Ching-Hsiang Hsu, Ruei-Ling Lin | 2003-05-20 |
| 6555474 | Method of forming a protective layer included in metal filled semiconductor features | Cheng-Lin Huang, Minghsing Tsai, Winston Shue | 2003-04-29 |
| 6548856 | Vertical stacked gate flash memory device | Chrong-Jung Lin, Shui-Hung Chen | 2003-04-15 |
| 6507066 | Highly reliable flash memory structure with halo source | Ching-Hsiang Hsu, Steve S. Chung | 2003-01-14 |
| 6476460 | Stacked gate MOS structure for multiple voltage power supply applications | Jin-Yuan Lee, Choe-San Yoo | 2002-11-05 |
| 6455330 | Methods to create high-k dielectric gate electrodes with backside cleaning | Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen | 2002-09-24 |
| 6440833 | Method of protecting a copper pad structure during a fuse opening procedure | Tze-Liang Lee | 2002-08-27 |
| 6436771 | Method of forming a semiconductor device with multiple thickness gate dielectric layers | Syun-Ming Jang, Chen-Hua Yu | 2002-08-20 |
| 6423625 | Method of improving the bondability between Au wires and Cu bonding pads | Syun-Ming Jang, Chen-Hua Yu, Chung-Shi Liu, Jane-Bai Lai | 2002-07-23 |
| 6387775 | Fabrication of MIM capacitor in copper damascene process | Syun-Ming Jang | 2002-05-14 |
| 6368952 | Diffusion inhibited dielectric structure for diffusion enhanced conductor layer | Syun-Ming Jang | 2002-04-09 |
| 6355962 | CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region | Shyh-Chyi Wong | 2002-03-12 |