Issued Patents All Time
Showing 101–125 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6346729 | Pseudo silicon on insulator MOSFET device | Jin-Yuan Lee, Chue-San Yoo | 2002-02-12 |
| 6339029 | Method to form copper interconnects | Chen-Hua Yu | 2002-01-15 |
| 6281545 | Multi-level, split-gate, flash memory cell | Di-Son Kuo, Ching-Hsiang Hsu, Ruei-Ling Lin | 2001-08-28 |
| 6271570 | Trench-free buried contact | Kuo-Ching Huang, Yean-Kuen Fang, Jhon Jhy Liaw, Cheng-Ming Wu, Dun-Nian Yaung | 2001-08-07 |
| 6258641 | OTP (open trigger path) latchup scheme using triple and buried well for sub-quarter micron transistors | Shyh-Chyi Wong | 2001-07-10 |
| 6245675 | 3D reservoir to improve electromigration resistance of tungsten plug | Shau-Lin Shue | 2001-06-12 |
| 6222214 | Plug structure and process for forming stacked contacts and metal contacts on static random access memory thin film transistors | Shou-Gwo Wuu, Chung-Hui Su, Chen-Jong Wang | 2001-04-24 |
| 6218286 | Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process | Chung-Hui Su, Shou-Gwo Wuu, Chen-Jong Wang | 2001-04-17 |
| 6201273 | Structure for a double wall tub shaped capacitor | Chen-Jong Wang | 2001-03-13 |
| 6184155 | Method for forming a ultra-thin gate insulator layer | Mo Yu, Syun-Ming Jang | 2001-02-06 |
| 6181542 | Method of making a stack-polysilicon capacitor-coupled dual power supply input/output protection circuit | Shyh-Chyi Wong | 2001-01-30 |
| 6174754 | Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors | Jin-Yuan Lee, Boon-Khim Liew | 2001-01-16 |
| 6166410 | MONOS flash memory for multi-level logic and method thereof | Ruei-Ling Lin, Ching-Hsiang Hsu | 2000-12-26 |
| 6136638 | Process technology architecture of embedded DRAM | Jin-Yuan Lee | 2000-10-24 |
| 6124618 | Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor | Shyh-Chyi Wong | 2000-09-26 |
| 6110822 | Method for forming a polysilicon-interconnect contact in a TFT-SRAM | Kuo-Ching Huang, Yean-Kuen Fang, Dun-Nian Yaung | 2000-08-29 |
| 6093606 | Method of manufacture of vertical stacked gate flash memory device | Chrong-Jung Lin, Shui-Hung Chen | 2000-07-25 |
| 6093617 | Process to fabricate hemispherical grain polysilicon | Chung-Hui Su | 2000-07-25 |
| 6093616 | Method of manufacture of stacked gate MOS structure for multiple voltage power supply applications | Jin-Yuan Lee, Chue-San Yoo | 2000-07-25 |
| 6090696 | Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures | Syun-Ming Jang | 2000-07-18 |
| 6087219 | Highly reliable flash memory structure with halo source | Ching-Hsiang Hsu, Steve S. Chung | 2000-07-11 |
| 6083795 | Large angle channel threshold implant for improving reverse narrow width effect | Ching-Hsiang Hsu | 2000-07-04 |
| 6080647 | Process to form a trench-free buried contact | Kuo-Ching Huang, Yean-Kuen Fang, Jhon Jhy Liaw, Cheng-Ming Wu, Dun-Nian Yaung | 2000-06-27 |
| 6078087 | SRAM memory device with improved performance | Kuo-Ching Huang, Yean-Kuen Fang, Cheng-Yeh Shih, Dun-Nian Yaung | 2000-06-20 |
| 6071783 | Pseudo silicon on insulator MOSFET device | Jin-Yuan Lee, Chue-San Yoo | 2000-06-06 |