Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6653709 | CMOS output circuit with enhanced ESD protection using drain side implantation | Yi-Hsu Wu, Hung-Der Su, Jian-Hsing Lee | 2003-11-25 |
| 6444511 | CMOS output circuit with enhanced ESD protection using drain side implantation | Yi-Hsu Wu, Hung-Der Su, Jian-Hsing Lee | 2002-09-03 |
| 6207479 | Place and route method for integrated circuit design | Jing-Meng Liu | 2001-03-27 |
| 6174754 | Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors | Jin-Yuan Lee, Mong-Song Liang | 2001-01-16 |
| 6117737 | Reduction of a hot carrier effect by an additional furnace anneal increasing transient enhanced diffusion for devices comprised with low temperature spacers | Jyh-Haur Wang | 2000-09-12 |