Issued Patents All Time
Showing 51–75 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7453149 | Composite barrier layer | Cheng-Lin Huang, Ching-Hua Hsieh, Hsien-Ming Lee, Shing-Chyang Pan, Chao-Hsien Peng +3 more | 2008-11-18 |
| 7443029 | Adhesion of copper and etch stop layer for copper alloy | Jing-Cheng Lin, Ching-Hua Hsieh, Shau-Lin Shue | 2008-10-28 |
| 7410854 | Method of making FUSI gate and resulting structure | Liang-Gi Yao, Hun-Jan Tao, Shih-Chang Chen | 2008-08-12 |
| 7402866 | Backside contacts for MOS devices | Hun-Jan Tao | 2008-07-22 |
| 7375040 | Etch stop layer | Simon Su-Horng Lin, Weng Chang, Syun-Ming Jang | 2008-05-20 |
| 7357838 | Relaxed silicon germanium substrate with low defect density | Chun-Chieh Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2008-04-15 |
| 7351994 | Noble high-k device | Liang-Gi Yao, Tien-Chih Chang, Ming-Fang Wang, Shih-Chang Chen | 2008-04-01 |
| 7253524 | Copper interconnects | Zhen-Cheng Wu, Tzu-Jen Chou, Weng Chang, Yung-Cheng Lu, Syun-Ming Jang | 2007-08-07 |
| 7247915 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology | Chih-Wei Chang, Mei-Yun Wang, Shau-Lin Shue | 2007-07-24 |
| 7238989 | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement | Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Chenming Hu | 2007-07-03 |
| 7215024 | Barrier-less integration with copper alloy | Jing-Cheng Lin, Cheng-Lin Huang, Ching-Hua Hsieh, Shau-Lin Shue | 2007-05-08 |
| 7202162 | Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials | Jing-Cheng Lin, Chao-Hsien Peng, Shau-Lin Shue | 2007-04-10 |
| 7202142 | Method for producing low defect density strained -Si channel MOSFETS | Kuen-Chyr Lee, Liang-Gi Yao, Shih-Chang Chen | 2007-04-10 |
| 7151052 | Multiple etch-stop layer deposition scheme and materials | Tai-Chun Huang, Chih-Hsiang Yao, Kuan-Shou Chi, Chin-Chiu Hsia | 2006-12-19 |
| 7115974 | Silicon oxycarbide and silicon carbonitride based materials for MOS devices | Zhen-Cheng Wu, Hung Chun Tsai, Da-Wen Lin, Weng Chang, Shwang-Ming Cheng | 2006-10-03 |
| 7105439 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology | Chih-Wei Chang, Mei-Yun Wang, Shau-Lin Shue | 2006-09-12 |
| 7105393 | Strained silicon layer fabrication with reduced dislocation defect density | Liang-Gi Yao, Tien-Chih Chang, CC Lin, Shin-Chang Chen | 2006-09-12 |
| 7071093 | Integrated treatment method for obtaining robust low dielectric constant materials | Yung-Cheng Lu, Huilin Chang | 2006-07-04 |
| 7012009 | Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process | Kuen-Chyr Lee, Liang-Gi Yao, Tien-Chih Chang, Chia-Lin Chen, Shih-Chang Chen | 2006-03-14 |
| 6995471 | Self-passivated copper interconnect structure | Shau-Lin Shue | 2006-02-07 |
| 6982208 | Method for producing high throughput strained-Si channel MOSFETS | Kuen-Chyr Lee, Liang-Gi Yao, Shih-Chang Chen | 2006-01-03 |
| 6967155 | Adhesion of copper and etch stop layer for copper alloy | Jing-Cheng Lin, Ching-Hua Hsieh, Shau-Lin Shue | 2005-11-22 |
| 6955952 | Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement | Yee-Chia Yeo, Chun-Chieh Lin, Fu-Liang Yang, Chenming Hu | 2005-10-18 |
| 6943111 | Barrier free copper interconnect by multi-layer copper seed | Jing-Cheng Lin, Cheng-Lin Huang, Winston Shue | 2005-09-13 |
| 6936530 | Deposition method for Si-Ge epi layer on different intermediate substrates | Liang-Gi Yao, Kuen-Chyr Lee, Shih-Chang Chen | 2005-08-30 |