Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387792 | Memory device and operating method thereof | — | 2025-08-12 |
| 11139165 | Staggered-type tunneling field effect transistor | E. Ray Hsieh, Kuan-Yu Chang | 2021-10-05 |
| 11133182 | Staggered-type tunneling field effect transistor | E. Ray Hsieh, Kuan-Yu Chang | 2021-09-28 |
| 11133183 | Staggered-type tunneling field effect transistor | E. Ray Hsieh, Kuan-Yu Chang | 2021-09-28 |
| 11133184 | Staggered-type tunneling field effect transistor | E. Ray Hsieh, Kuan-Yu Chang | 2021-09-28 |
| 10756267 | Nonvolatile memory comprising variable resistance transistors and method for operating the same | E-Ray Hsieh | 2020-08-25 |
| 10504721 | Staggered-type tunneling field effect transistor | E. Ray Hsieh, Kuan-Yu Chang | 2019-12-10 |
| 10127993 | Dielectric fuse memory circuit and operation method thereof | E-Ray Hsieh, Zhi-Hong Huang | 2018-11-13 |
| 9735267 | Structure and formation method of semiconductor device structure | E-Ray Hsieh, Yi-Hsien Lin | 2017-08-15 |
| 9577078 | Structure and formation method of semiconductor device structure | E-Ray Hsieh, Yu Zhao, Samuel C. Pan | 2017-02-21 |
| 9548398 | NAND type variable resistance random access memory and methods | E-Ray Hsieh | 2017-01-17 |
| 9336869 | Nonvoltile resistance memory and its operation thereof | E-Ray Hsieh | 2016-05-10 |
| 6746883 | Direct determination of interface traps in MOS devices | Shang-Jr Chen, Chien-Kuo Yang, Der-Yuan Wu | 2004-06-08 |
| 6507066 | Highly reliable flash memory structure with halo source | Ching-Hsiang Hsu, Mong-Song Liang | 2003-01-14 |
| 6087219 | Highly reliable flash memory structure with halo source | Ching-Hsiang Hsu, Mong-Song Liang | 2000-07-11 |
| 5818085 | Body contact for a MOSFET device fabricated in an SOI layer | Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang | 1998-10-06 |
| 5728613 | Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor | Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang | 1998-03-17 |
| 5705839 | Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology | Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang | 1998-01-06 |
| 5610087 | Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer | Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang | 1997-03-11 |
| 5573961 | Method of making a body contact for a MOSFET device fabricated in an SOI layer | Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang | 1996-11-12 |
| 5567631 | Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology | Ching-Hsiang Hsu, Shyh-Chyi Wong, Mong-Song Liang | 1996-10-22 |