Issued Patents All Time
Showing 151–175 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5801415 | Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors | Jin-Yuan Lee | 1998-09-01 |
| 5796150 | High-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel | Shou-Gwo Wuu, Kan-Yuan Lee | 1998-08-18 |
| 5796135 | Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a single semiconductor chip | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1998-08-18 |
| 5792684 | Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip | Jin-Yuan Lee | 1998-08-11 |
| 5759892 | Formation of self-aligned capacitor contact module in stacked cyclindrical dram cell | Chen-Jong Wang | 1998-06-02 |
| 5759888 | Method for fabricating a DRAM cell with a Y shaped storage capacitor | Chen-Jong Wang | 1998-06-02 |
| 5731232 | Method for concurrently making thin-film-transistor (TFT) gate electrodes and ohmic contacts at P/N junctions for TFT-static random | Shou-Gwo Wuu | 1998-03-24 |
| 5728613 | Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor | Ching-Hsiang Hsu, Steve S. Chung, Shyh-Chyi Wong | 1998-03-17 |
| 5723374 | Method for forming dielectric spacer to prevent poly stringer in stacked capacitor DRAM technology | Julie Huang | 1998-03-03 |
| 5719079 | Method of making a semiconductor device having high density 4T SRAM in logic with salicide process | Chue-San Yoo, Jin-Yuan Lee | 1998-02-17 |
| 5716881 | Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1998-02-10 |
| 5714412 | Multi-level, split-gate, flash memory cell and method of manufacture thereof | Di-Son Kuo, Ching-Hsiang Hsu, Ruei-Ling Lin | 1998-02-03 |
| 5712201 | Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip | Jin-Yuan Lee, Chue-San Yoo | 1998-01-27 |
| 5707897 | Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors | Jin-Yuan Lee | 1998-01-13 |
| 5705839 | Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology | Ching-Hsiang Hsu, Shyh-Chyi Wong, Steve S. Chung | 1998-01-06 |
| 5702989 | Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column | Chen-Jong Wang | 1997-12-30 |
| 5702988 | Blending integrated circuit technology | — | 1997-12-30 |
| 5693974 | Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron MOSFETS | Ching-Hsiang Hsu | 1997-12-02 |
| 5686335 | Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel | Shou-Gwo Wuu, Kan-Yuan Lee | 1997-11-11 |
| 5679591 | Method of making raised-bitline contactless trenched flash memory cell | Ruei-Ling Lin, Ching-Hsiang Hsu | 1997-10-21 |
| 5677557 | Method for forming buried plug contacts on semiconductor integrated circuits | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1997-10-14 |
| 5672896 | Three stage ESD protection device | Jin-Yuan Lee | 1997-09-30 |
| 5670431 | Method of forming an ultra thin dielectric film for a capacitor | Julie Huanga | 1997-09-23 |
| 5668038 | One step smooth cylinder surface formation process in stacked cylindrical DRAM products | Yuan-Chang Huang, Chen-Jong Wang | 1997-09-16 |
| 5668035 | Method for fabricating a dual-gate dielectric module for memory with embedded logic technology | Chung Hsin Fang, Julie Huang, Chen-Jong Wang | 1997-09-16 |