Issued Patents All Time
Showing 126–150 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6071773 | Process for fabricating a DRAM metal capacitor structure for use in an integrated circuit | Jin-Yuan Lee | 2000-06-06 |
| 6054348 | Self-aligned source process | Ruei-Ling Lin, Ching-Hsiang Hsu | 2000-04-25 |
| 6054344 | OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors | Shyh-Chyi Wong | 2000-04-25 |
| 6051458 | Drain and source engineering for ESD-protection transistors | Shyh-Chyi Wong | 2000-04-18 |
| 6022775 | High effective area capacitor for high density DRAM circuits using silicide agglomeration | Chaochieh Tsai | 2000-02-08 |
| 6001731 | Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process | Chung-Hui Su, Shou-Gwo Wuu, Chen-Jong Wang | 1999-12-14 |
| 5994177 | Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor | Shyh-Chyi Wong | 1999-11-30 |
| 5953606 | Method for manufacturing a TFT SRAM memory device with improved performance | Kuo-Ching Huang, Yean-Kuen Fang, Cheng-Yeh Shih, Dun-Nian Yaung | 1999-09-14 |
| 5923974 | Method of manufacture of memory device with high coupling ratio | Ching-Hsiang Hsu, Ruei-Ling Lin | 1999-07-13 |
| 5920111 | CMOS OP-AMP circuit using BJT as input stage | Shyh-Chyi Wong | 1999-07-06 |
| 5900658 | Logic and single level polysilicon DRAM devices fabricated on the same semiconductor chip | Jin-Yuan Lee, Chue-San Yoo | 1999-05-04 |
| 5885865 | Method for making low-topography buried capacitor by a two stage etching process and device made | Julie Huang, Tse-Liang Ying, Chen-Jong Wang | 1999-03-23 |
| 5877523 | Multi-level split- gate flash memory cell | Di-Son Kuo, Ching-Hsiang Hsu, Ruei-Ling Lin | 1999-03-02 |
| 5866451 | Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic | Chue-San Yoo, Jin-Yuan Lee | 1999-02-02 |
| 5867087 | Three dimensional polysilicon resistor for integrated circuits | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1999-02-02 |
| 5861634 | Charge collector structure for detecting radiation induced charge during integrated circuit processing | Ching-Hsiang Hsu, Chrong-Jung Lin | 1999-01-19 |
| 5858830 | Method of making dual isolation regions for logic and embedded memory devices | Chue-San Yoo | 1999-01-12 |
| 5856220 | Method for fabricating a double wall tub shaped capacitor | Chen-Jong Wang | 1999-01-05 |
| 5851881 | Method of making monos flash memory for multi-level logic | Ruei-Ling Lin, Ching-Hsiang Hsu | 1998-12-22 |
| 5846860 | Method of making buried contact in DRAM technology | Chun-Yi Shih, Julie Huang | 1998-12-08 |
| 5843817 | Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits | Jin-Yuan Lee | 1998-12-01 |
| 5834806 | Raised-bitline, contactless, trenched, flash memory cell | Ruei-Ling Lin, Ching-Hsiang Hsu | 1998-11-10 |
| 5818085 | Body contact for a MOSFET device fabricated in an SOI layer | Ching-Hsiang Hsu, Shyh-Chyi Wong, Steve S. Chung | 1998-10-06 |
| 5811331 | Formation of a stacked cylindrical capacitor module in the DRAM technology | Tse-Liang Ying | 1998-09-22 |
| 5804858 | Body contacted SOI MOSFET | Ching-Hsiang Hsu | 1998-09-08 |