Issued Patents All Time
Showing 176–200 of 211 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5668380 | Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance | Shou-Gwo Wuu, Chung-Hui Su, Chen-Jong Wang | 1997-09-16 |
| 5656546 | Self-aligned tin formation by N.sub.2.sup.+ implantation during two-step annealing Ti-salicidation | Chii-Wen Chen | 1997-08-12 |
| 5654231 | Method of eliminating buried contact trench in SRAM technology | Jin-Yuan Lee, Chun-Yi Shih | 1997-08-05 |
| 5652174 | Unified stacked contact process for static random access memory (SRAM) having polysilicon load resistors | Shou-Gwo Wuu, Chung-Hui Su, Chen-Jong Wang | 1997-07-29 |
| 5646061 | Two-layer polysilicon process for forming a stacked DRAM capacitor with improved doping uniformity and a controllable shallow junction contact | Chen-Jong Wang | 1997-07-08 |
| 5646435 | Method for fabricating CMOS field effect transistors having sub-quarter micrometer channel lengths with improved short channel effect characteristics | Charles C. Hsu | 1997-07-08 |
| 5644269 | Cascode MOS current mirror with lateral bipolar junction transistor to enhance ouput signal swing | Shyh-Chyi Wong | 1997-07-01 |
| 5623153 | Sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains | Charles C. Hsu | 1997-04-22 |
| 5616951 | Dielectric as load resistor in 4T SRAM | — | 1997-04-01 |
| 5614430 | Anti-punchthrough ion implantation for sub-half micron channel length MOSFET devices | Jin-Yuan Lee | 1997-03-25 |
| 5614424 | Method for fabricating an accumulated-base bipolar junction transistor | Shyh-Chyi Wong | 1997-03-25 |
| 5610087 | Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer | Ching-Hsiang Hsu, Shyh-Chyi Wong, Steve S. Chung | 1997-03-11 |
| 5607879 | Method for forming buried plug contacts on semiconductor integrated circuits | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1997-03-04 |
| 5607874 | Method for fabricating a DRAM cell with a T shaped storage capacitor | Chen-Jong Wang | 1997-03-04 |
| 5605853 | Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells | Chue-San Yoo, Jin-Yuan Lee | 1997-02-25 |
| 5593911 | Method of making ESD protection circuit with three stages | Jin-Yuan Lee | 1997-01-14 |
| 5591650 | Method of making a body contacted SOI MOSFET | Ching-Hsiang Hsu | 1997-01-07 |
| 5587696 | High resistance polysilicon resistor for integrated circuits and method of fabrication thereof | Chung-Hui Su, Shou-Gwo Wuu, Chen-Jong Wang | 1996-12-24 |
| 5576243 | Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors | Shou-Gwo Wuu, Chung-Hui Su, Chen-Jong Wang | 1996-11-19 |
| 5573961 | Method of making a body contact for a MOSFET device fabricated in an SOI layer | Ching-Hsiang Hsu, Shyh-Chyi Wong, Steve S. Chung | 1996-11-12 |
| 5567631 | Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology | Ching-Hsiang Hsu, Shyh-Chyi Wong, Steve S. Chung | 1996-10-22 |
| 5547892 | Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors | Shou-Gwo Wuu, Chung-Hui Su, Chen-Jong Wang | 1996-08-20 |
| 5545584 | Unified contact plug process for static random access memory (SRAM) having thin film transistors | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1996-08-13 |
| 5545579 | Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains | Charles C. Hsu | 1996-08-13 |
| 5545585 | Method of making a dram circuit with fin-shaped stacked capacitors | Chen-Jong Wang, Shou-Gwo Wuu, Chung-Hui Su | 1996-08-13 |