Issued Patents All Time
Showing 26–50 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10811374 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin +2 more | 2020-10-20 |
| 10566237 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Tsang-Jiuh Wu +3 more | 2020-02-18 |
| 10510604 | Semiconductor device and method | Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Wen-Chih Chiou | 2019-12-17 |
| 10510641 | Semiconductor device having backside interconnect structure on through substrate via and method of forming the same | Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih +3 more | 2019-12-17 |
| 10340205 | Through substrate vias with improved connections | Jing-Cheng Lin | 2019-07-02 |
| 10269761 | Semiconductor device and method | Cheng-Chun Tsai, Hung-Pin Chang, Yi-Hsiu Chen, Wen-Chih Chiou | 2019-04-23 |
| 10170396 | Through via structure extending to metallization layer | Yi-Hsiu Chen, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu | 2019-01-01 |
| 10163705 | Profile of through via protrusion in 3DIC interconnect | Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Tsang-Jiuh Wu +3 more | 2018-12-25 |
| 10163709 | Semiconductor device and method | Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Wen-Chih Chiou | 2018-12-25 |
| 10157866 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin +2 more | 2018-12-18 |
| 10074595 | Self-alignment for redistribution layer | Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen +2 more | 2018-09-11 |
| 9953920 | Interconnect structure and method | Hsin-Yu Chen, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu +1 more | 2018-04-24 |
| 9847256 | Methods for forming a device having a capped through-substrate via structure | Yung-Chi Lin, Yen-Hung Chen, Yin Chen, Ebin Liao, Tsang-Jiuh Wu +1 more | 2017-12-19 |
| 9847255 | TSV formation processes using TSV-last approach | Jing-Cheng Lin, Yung-Chi Lin | 2017-12-19 |
| 9799694 | Backside through vias in a bonded structure | Weng-Jin Wu, Hung-Pin Chang, Wen-Chih Chiou, Chen-Hua Yu | 2017-10-24 |
| 9786580 | Self-alignment for redistribution layer | Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen +2 more | 2017-10-10 |
| 9773701 | Methods of making integrated circuits including conductive structures through substrates | Yuan-Hung Liu, Pei-Ching Kuo, Ming-Tsu Chung, Hsin-Yu Chen, Tsang-Jiuh Wu +1 more | 2017-09-26 |
| 9754831 | Dummy structure for chip-on-wafer-on-substrate | Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu +2 more | 2017-09-05 |
| 9704783 | Through substrate vias with improved connections | Jing-Cheng Lin | 2017-07-11 |
| 9679859 | Interconnect structure and method of forming same | Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin +2 more | 2017-06-13 |
| 9633929 | TSV formation | Shin-Puu Jeng, Wen-Chih Chiou | 2017-04-25 |
| 9601410 | Semiconductor device and method | Cheng-Chun Tsai, Hung-Pin Chang, Yi-Hsiu Chen, Wen-Chih Chiou | 2017-03-21 |
| 9583465 | Three dimensional integrated circuit structure and manufacturing method of the same | Kuang-Wei Cheng, Yi-Hsiu Chen, Wen-Chih Chiou | 2017-02-28 |
| 9514986 | Device with capped through-substrate via structure | Yung-Chi Lin, Yen-Hung Chen, Yin Chen, Ebin Liao, Tsang-Jiuh Wu +1 more | 2016-12-06 |
| 9449898 | Semiconductor device having backside interconnect structure through substrate via and method of forming the same | Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih +3 more | 2016-09-20 |