Issued Patents All Time
Showing 51–75 of 111 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773671 | Material composition and process for mitigating assist feature pattern transfer | Meng CHEN, Chen-Hau Wu, Meng-Wei Chen, Kuei-Shun Chen, Yu-Chin Huang +2 more | 2017-09-26 |
| 9754073 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ru-Gun Liu, Lee-Chung Lu | 2017-09-05 |
| 9728407 | Method of forming features with various dimensions | Chi-Cheng Hung, Chih-Ming Lai, Wei-Liang Lin, Chun-Kuang Chen, Ru-Gun Liu | 2017-08-08 |
| 9716032 | Via-free interconnect structure with self-aligned metal line interconnections | Yu-Po Tang, Shih-Ming Chang, Ru-Gun Liu | 2017-07-25 |
| 9684236 | Method of patterning a film layer | Kuan-Hsin Lo, Shih-Ming Chang, Wei-Liang Lin, Joy Cheng, Chun-Kuang Chen +5 more | 2017-06-20 |
| 9627310 | Semiconductor device with self-aligned interconnects | Shih-Ming Chang, Tsong-Hua Ou, Ru-Gun Liu, Fang-Yu Fan, Yuan-Te Hou | 2017-04-18 |
| 9613850 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ru-Gun Liu | 2017-04-04 |
| 9594866 | Method for checking and fixing double-patterning layout | Dio Wang, Huang-Yu Chen, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu | 2017-03-14 |
| 9581900 | Self aligned patterning with multiple resist layers | Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Shih-Ming Chang | 2017-02-28 |
| 9564327 | Method for forming line end space structure using trimmed photo resist | Chia-Ying Lee, Jyu-Horng Shieh, Ming-Feng Shieh, Shih-Ming Chang, Chih-Ming Lai +1 more | 2017-02-07 |
| 9530727 | Conductive line routing for multi-patterning technology | You-Cheng Xiao, Wei Min Chan | 2016-12-27 |
| 9524939 | Multiple edge enabled patterning | Ming-Feng Shieh, Ya Hui Chang, Ru-Gun Liu, Tsong-Hua Ou, Burn Jeng Lin | 2016-12-20 |
| 9502261 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2016-11-22 |
| 9449140 | Conflict detection for self-aligned multiple patterning compliance | Chin-Chang Hsu, HungLung Lin, Ying-Yu Shen, Wen-Ju Yang | 2016-09-20 |
| 9448470 | Method for making a mask with a phase bar in an integrated circuit design layout | Ru-Gun Liu, Shou-Yen Chou, Hoi-Tou Ng, Yi-Yin Chen | 2016-09-20 |
| 9418196 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ru-Gun Liu, Lee-Chung Lu | 2016-08-16 |
| 9405879 | Cell boundary layout | Yen-Sen Wang, Ting Yu Chen, Ming-Yi Lin, Chen-Hung Lu | 2016-08-02 |
| 9390223 | Method of determining whether a layout is colorable | Wen-Li Cheng, Ming-Hui Chih, Chia-Ping Chiang, Tsong-Hua Ou, Wen-Chun Huang +1 more | 2016-07-12 |
| 9362119 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu +1 more | 2016-06-07 |
| 9362169 | Self-aligned semiconductor fabrication with fosse features | Shih-Ming Chang, Chih-Ming Lai, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau | 2016-06-07 |
| 9356021 | Self-alignment for two or more layers and methods of forming same | Shih-Ming Chang, Ru-Gun Liu, Ming-Feng Shieh, Chih-Ming Lai, Tsai-Sheng Gau | 2016-05-31 |
| 9337083 | Multi-layer metal contacts | Ming-Feng Shieh, Wen-Hung Tseng, Chih-Ming Lai, Tsai-Sheng Gau, Ru-Gun Liu | 2016-05-10 |
| 9305841 | Method of patterning a feature of a semiconductor device | Yen-Chun Huang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau | 2016-04-05 |
| 9292645 | Layout optimization for integrated circuit design | Huang-Yu Chen, Yuan-Te Hou, Yu-Hsiang Kao, Ru-Gun Liu, Lee-Chung Lu | 2016-03-22 |
| 9287125 | Multiple edge enabled patterning | Ming-Feng Shieh, Ya Hui Chang, Ru-Gun Liu, Tsong-Hua Ou, Burn Jeng Lin | 2016-03-15 |