Issued Patents All Time
Showing 26–50 of 111 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10930505 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu +1 more | 2021-02-23 |
| 10817635 | Multiple patterning method for semiconductor devices | Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wang | 2020-10-27 |
| 10790155 | Method of manufacturing semiconductor devices | Ru-Gun Liu, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen, Chin-Hsiang Lin | 2020-09-29 |
| 10784626 | Electrical connector | Li-Sen Chen, Cheng-Hsiang Hsueh | 2020-09-22 |
| 10770304 | Hybrid double patterning method for semiconductor manufacture | Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu | 2020-09-08 |
| 10769007 | Computing node failure and health prediction for cloud-based data center | Murali Mohan Chintalapati, Youjiang Wu, Randolph Yao, Qingwei Lin, Yingnong Dang | 2020-09-08 |
| 10763113 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ru-Gun Liu | 2020-09-01 |
| 10748767 | Method for forming conductive lines | Yung-Sung Yen, Ru-Gun Liu | 2020-08-18 |
| 10678142 | Optical proximity correction and photomasks | Dong-Yo Jheng, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu | 2020-06-09 |
| 10665467 | Spacer etching process for integrated circuit design | Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee +6 more | 2020-05-26 |
| 10483120 | Hybrid double patterning method for semiconductor manufacture | Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu | 2019-11-19 |
| 10418252 | Fin-like field effect transistor patterning methods for increasing process margins | Chin-Yuan Tseng, Wei-Liang Lin, Hsin-Chih Chen, Shi Ning Ju, Yung-Sung Yen +1 more | 2019-09-17 |
| 10410913 | Multi-layer metal contacts | Ming-Feng Shieh, Wen-Hung Tseng, Chih-Ming Lai, Tsai-Sheng Gau, Ru-Gun Liu | 2019-09-10 |
| 10410863 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu +1 more | 2019-09-10 |
| 10388523 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ru-Gun Liu | 2019-08-20 |
| 10382292 | Quality assessment and decision recommendation for continuous deployment of cloud infrastructure components | Pankaj Kumar Singh, Sree Krishna Chaitanya Vadrevu, Ze Li, Murali Mohan Chintalapati, Yingnong Dang | 2019-08-13 |
| 10274829 | Multiple patterning decomposition and manufacturing methods for IC | Wen-Li Cheng, Pai-Wei Wang, Ru-Gun Liu, Chih-Ming Lai | 2019-04-30 |
| 10276377 | Method for patterning interconnects | Yung-Sung Yen, Yu-Hsun Chen, Chen-Hau Wu, Chun-Kuang Chen, Ta-Ching Yu +2 more | 2019-04-30 |
| 10276394 | Hybrid double patterning method for semiconductor manufacture | Wen-Li Cheng, Dong-Yo Jheng, Chih-Ming Lai, Ru-Gun Liu | 2019-04-30 |
| 10163634 | Method for forming conductive lines | Yung-Sung Yen, Ru-Gun Liu | 2018-12-25 |
| 10083270 | Target optimization method for improving lithography printability | Shih-Ming Chang, Shuo-Yen Chou, Ru-Gun Liu | 2018-09-25 |
| 10078718 | Multiple patterning method for semiconductor devices | Chih-Ming Lai, Ru-Gun Liu, Wen-Chun Huang, Wen-Li Cheng, Pai-Wei Wan | 2018-09-18 |
| 10032664 | Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography | Shih-Ming Chang, Chih-Ming Lai, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau | 2018-07-24 |
| 9984876 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ru-Gun Liu | 2018-05-29 |
| 9852908 | Methods for integrated circuit design and fabrication | Tsong-Hua Ou, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu +1 more | 2017-12-26 |