Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11940737 | Method of fabricating reticle | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2024-03-26 |
| 11003091 | Method of fabricating reticle | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2021-05-11 |
| 10867933 | Method for forming semiconductor device structure with overlay grating | Long Chen, Jia-Hong Chu, Chi-Wen Lai, Chia-Ching Liang, Kai-Hsiung Chen +4 more | 2020-12-15 |
| 10734325 | Method for forming semiconductor device structure with overlay grating | Long Chen, Jia-Hong Chu, Chi-Wen Lai, Chia-Ching Liang, Kai-Hsiung Chen +4 more | 2020-08-04 |
| 10534272 | Method of fabricating reticle | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2020-01-14 |
| 10461037 | Method for forming semiconductor device structure with overlay grating | Long Chen, Jia-Hong Chu, Chi-Wen Lai, Chia-Ching Liang, Kai-Hsiung Chen +4 more | 2019-10-29 |
| 10146141 | Lithography process and system with enhanced overlay quality | Chi-Cheng Hung, Wei-Liang Lin, Yung-Sung Yen, Chun-Kuang Chen, Ru-Gun Liu +6 more | 2018-12-04 |
| 10073354 | Exposure method of wafer substrate, manufacturing method of semiconductor device, and exposure tool | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2018-09-11 |
| 9773671 | Material composition and process for mitigating assist feature pattern transfer | Meng CHEN, Chen-Hau Wu, Kuei-Shun Chen, Yu-Chin Huang, Li-Hsiang Lai +2 more | 2017-09-26 |
| 9129974 | Enhanced FinFET process overlay mark | Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen | 2015-09-08 |
| 8850369 | Metal cut process flow | Yuan-Hsiang Lung, Kuei-Shun Chen, Chia-Ying Lee | 2014-09-30 |
| 8840796 | Integrated circuit method with triple patterning | Chia-Chu Liu, Kuei-Shun Chen | 2014-09-23 |
| 8822343 | Enhanced FinFET process overlay mark | Chi-Wen Hsieh, Chi-Kang Chang, Chia-Chu Liu, Kuei-Shun Chen | 2014-09-02 |
| 8716139 | Method of patterning a semiconductor device | George Liu, Kuei-Shun Chen | 2014-05-06 |
| 8562843 | Integrated circuit method with triple patterning | Chia-Chu Liu, Kuei-Shun Chen | 2013-10-22 |
| 8455982 | Overlay mark enhancement feature | Chi-Chuang Lee, Chung-Hsien Lin | 2013-06-04 |
| 8237297 | System and method for providing alignment mark for high-k metal gate process | Kuei-Shun Chen, George Liu, Jiann Yuan Huang, Chia-Ching Lin | 2012-08-07 |
| 8203836 | Cover structure | Hsin-Chih Chen, Yun-Chung Chang, Hsin-Chi Huang, Li-Wen Hsu, Ju-Il Lee | 2012-06-19 |
| 8148232 | Overlay mark enhancement feature | Chi-Chuang Lee, Chung-Hsien Lin | 2012-04-03 |
| 7097945 | Method of reducing critical dimension bias of dense pattern and isolation pattern | Ching-Yu Chang, Hsin-Huei Chen | 2006-08-29 |