Issued Patents All Time
Showing 326–350 of 549 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9698135 | Mechanisms for forming package structure | Po-Hao Tsai | 2017-07-04 |
| 9691706 | Multi-chip fan out package and methods of forming the same | Chen-Hua Yu, Jui-Pin Hung | 2017-06-27 |
| 9679783 | Molding wafer chamber | Chin-Chuan Chang, Jui-Pin Hung, Szu-Wei Lu, Shin-Puu Jeng, Chen-Hua Yu | 2017-06-13 |
| 9673098 | Methods of packaging semiconductor devices and structures thereof | Jui-Pin Hung, Yi-Hang Lin, Tsan-Hua Tung | 2017-06-06 |
| 9673181 | Package on package (PoP) bonding structures | Jui-Pin Hung, Po-Hao Tsai | 2017-06-06 |
| 9662872 | De-bonding and cleaning process and system | Ying-Ching Shih, Szu-Wei Lu | 2017-05-30 |
| 9666487 | Method for manufacturing germanium-based CMOS comprising forming silicon cap over PMOS region having a thickness less than that over NMOS region | Chen-Hua Yu | 2017-05-30 |
| 9662812 | Methods for molding integrated circuits | Chih-Hao Chen, Hsien-Wen Liu, Yi-Lin Tsai, Jui-Pin Hung | 2017-05-30 |
| 9653423 | Integrated circuit structure having dies with connectors | Cheng-Lin Huang | 2017-05-16 |
| 9646918 | Semiconductor device and method | Li-Hui Cheng, Po-Hao Tsai | 2017-05-09 |
| 9646942 | Mechanisms for controlling bump height variation | Po-Hao Tsai | 2017-05-09 |
| 9633934 | Semicondutor device and method of manufacture | Po-Hao Tsai, Li-Hui Cheng, Porter Chen | 2017-04-25 |
| 9633895 | Integrated fan-out structure with guiding trenches in buffer layer | Po-Hao Tsai, Feng-Cheng Hsu, Li-Hui Cheng, Jui-Pin Hung | 2017-04-25 |
| 9633924 | Package structure and method for forming the same | Chen-Hua Yu, Tsei-Chung Fu | 2017-04-25 |
| 9627346 | Underfill pattern with gap | Feng-Cheng Hsu, Hou-Ju Huang, Szu-Wei Lu | 2017-04-18 |
| 9620430 | Sawing underfill in packaging processes | Szu-Wei Lu, Ying-Da Wang, Li-Chung Kuo | 2017-04-11 |
| 9583420 | Semiconductor device and method of manufactures | Po-Hao Tsai, Li-Hui Cheng | 2017-02-28 |
| 9583424 | Integrated circuit structure and method for reducing polymer layer delamination | Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin | 2017-02-28 |
| 9583461 | Probing chips during package formation | Szu-Wei Lu | 2017-02-28 |
| 9570401 | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices | Po-Hao Tsai, Jui-Pin Hung | 2017-02-14 |
| 9570421 | Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure | Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu | 2017-02-14 |
| 9559072 | Metal bump joint structure | — | 2017-01-31 |
| 9553059 | Backside redistribution layer (RDL) structure | Po-Hao Tsai | 2017-01-24 |
| 9553000 | Interconnect structure for wafer level package | Chen-Hua Yu, Nai-Wei Liu, Jui-Pin Hung, Shin-Puu Jeng | 2017-01-24 |
| 9543170 | Semiconductor packages and methods of forming the same | Chen-Hua Yu, Po-Hao Tsai | 2017-01-10 |