Issued Patents All Time
Showing 26–50 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9484302 | Semiconductor devices and methods of manufacture thereof | Shin-Yi Yang, Ming-Han Lee, Hsien-Chang Wu | 2016-11-01 |
| 9466525 | Interconnect structures comprising flexible buffer layers | Chao-Hsien Peng, Hsin-Yen Huang, Shau-Lin Shue | 2016-10-11 |
| 9455184 | Aluminum interconnection apparatus | Ching-Fu Yeh | 2016-09-27 |
| 9425089 | Conductive element structure and method | Tai-I Yang, Hsiang-Wei Liu, Chia-Tien Wu, Tien-Lu Lin | 2016-08-23 |
| 9385029 | Method for forming recess-free interconnect structure | Chao-Hsien Peng, Shau-Lin Shue | 2016-07-05 |
| 9373586 | Copper etching integration scheme | Chih Wei Lu, Chung-Ju Lee, Tien-I Bao | 2016-06-21 |
| 9343400 | Dual damascene gap filling process | Shau-Lin Shue | 2016-05-17 |
| 9343356 | Back end of the line (BEOL) interconnect scheme | Chi-Liang Kuo, Tz-Jun Kuo | 2016-05-17 |
| 9330989 | System and method for chemical-mechanical planarization of a metal layer | Yung-Hsu Wu, Shih-Kang Fu, Hsin-Chieh Yao, Chung-Ju Lee, Hai-Ching Chen +1 more | 2016-05-03 |
| 9324608 | Method for via plating with seed layer | Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Ming-Han Lee | 2016-04-26 |
| 9318364 | Semiconductor device metallization systems and methods | Shau-Lin Shue, Keith Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang +3 more | 2016-04-19 |
| 9318439 | Interconnect structure and manufacturing method thereof | Shin-Yi Yang, Hsi-Wen Tien, Ming-Han Lee, Shau-Lin Shue | 2016-04-19 |
| 9281263 | Interconnect structure including a continuous conductive body | Ming-Han Lee, Hai-Ching Chen, Tien-I Bao, Chi-Lin Teng | 2016-03-08 |
| 9275960 | Integrated circuit formed using spacer-like copper deposition | Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee | 2016-03-01 |
| 9269668 | Interconnect having air gaps and polymer wrapped conductive lines | Shin-Yi Yang, Ming-Han Lee, Hsi-Wen Tien, Shau-Lin Shue | 2016-02-23 |
| 9252049 | Method for forming interconnect structure that avoids via recess | Chao-Hsien Peng, Tsung-Min Huang, Shau-Lin Shue | 2016-02-02 |
| 9219033 | Via pre-fill on back-end-of-the-line interconnect layer | Chao-Hsien Peng, Chi-Liang Kuo, Ming-Han Lee, Shau-Lin Shue | 2015-12-22 |
| 9177797 | Lithography using high selectivity spacers for pitch reduction | Yu-Sheng Chang, Chung-Ju Lee, Cheng-Hsiung Tsai, Yung-Hsu Wu, Hai-Ching Chen +5 more | 2015-11-03 |
| 9159579 | Lithography using multilayer spacer for reduced spacer footing | Chao-Hsien Peng, Shau-Lin Shue | 2015-10-13 |
| 9142505 | Method and apparatus for back end of line semiconductor device processing | Shin-Yi Yang, Ming-Han Lee, Ching-Fu Yeh, Pei-Yin Liou | 2015-09-22 |
| 9142509 | Copper interconnect structure and method for forming the same | Chen-Hua Yu, Shau-Lin Shue, Ching-Fu Yeh | 2015-09-22 |
| 9093501 | Interconnection wires of semiconductor devices | Sunil Kumar Singh, Hsin-Chieh Yao, Chung-Ju Lee | 2015-07-28 |
| 9054161 | Method of semiconductor integrated circuit fabrication | Ching-Fu Yeh, Chao-Hsien Peng, Hsien-Chang Wu | 2015-06-09 |
| 9054163 | Method for via plating with seed layer | Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Ming-Han Lee | 2015-06-09 |
| 9034756 | Integrated circuit interconnects and methods of making same | Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Ming-Han Lee | 2015-05-19 |