Issued Patents All Time
Showing 51–75 of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10032639 | Methods for improved critical dimension uniformity in a semiconductor device fabrication process | Chi-Cheng Hung, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen | 2018-07-24 |
| 10007177 | Method to define multiple layer patterns using double exposures | Ming-Huei Weng, Ching-Yu Chang | 2018-06-26 |
| 9997404 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee +4 more | 2018-06-12 |
| 9991132 | Lithographic technique incorporating varied pattern materials | Chin-Yuan Tseng, Chi-Cheng Hung, De-Fang Chen, Ru-Gun Liu, Tsai-Sheng Gau +1 more | 2018-06-05 |
| 9984876 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu | 2018-05-29 |
| 9911697 | Power strap structure for high performance and low current density | Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng +6 more | 2018-03-06 |
| 9814111 | Modular light control device and dimming control system | Ji Huang, Tung-Yu Chen | 2017-11-07 |
| 9793211 | Dual power structure with connection pins | Shih-Wei Peng, Chih-Ming Lai, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng +3 more | 2017-10-17 |
| 9754881 | Designed-based interconnect structure in semiconductor structure | Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Kam-Tou Sio, Tsong-Hua Ou +3 more | 2017-09-05 |
| 9728407 | Method of forming features with various dimensions | Ken-Hsien Hsieh, Chi-Cheng Hung, Chih-Ming Lai, Wei-Liang Lin, Ru-Gun Liu | 2017-08-08 |
| 9684236 | Method of patterning a film layer | Ken-Hsien Hsieh, Kuan-Hsin Lo, Shih-Ming Chang, Wei-Liang Lin, Joy Cheng +5 more | 2017-06-20 |
| 9613850 | Lithographic technique for feature cut by line-end shrink | Yung-Sung Yen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu | 2017-04-04 |
| 9560701 | Driving circuit and lamps | Po-Shen Chen, Feng-Ling Lin, Hui-Ying Chen, Tung-Yu Chen | 2017-01-31 |
| 9543406 | Structure and method for overlay marks | Hsien-Cheng Wang, Ming-Chang Wen, Yao-Ching Ku | 2017-01-10 |
| 9538594 | Lamp | Chien-Nan Yeh | 2017-01-03 |
| 9530660 | Multiple directed self-assembly patterning process | Chin-Yuan Tseng, Chi-Cheng Hung, Kuan-Hsin Lo, Ru-Gun Liu, Tsai-Sheng Gau +1 more | 2016-12-27 |
| 9449880 | Fin patterning methods for increased process margin | Chin-Yuan Tseng, Chi-Cheng Hung, Chih-Ming Lai, Huan-Just Lin, Ru-Gun Liu +2 more | 2016-09-20 |
| 9431297 | Method of forming an interconnect structure for a semiconductor device | Yung-Hsu Wu, Cheng-Hsiung Tsai, Yu-Sheng Chang, Chia-Tien Wu, Chung-Ju Lee +4 more | 2016-08-30 |
| 9418868 | Method of fabricating semiconductor device with reduced trench distortions | Yung-Sung Yen, Chung-Ju Lee, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2016-08-16 |
| 9412649 | Method of fabricating semiconductor device | Yung-Sung Yen, Chung-Ju Lee, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen +4 more | 2016-08-09 |
| 9383657 | Method and structure for lithography processes with focus monitoring and control | Jhih-Yu Wang, Chien-Yu Li, Iu-Ren Chen, Chi-Cheng Hung, Wei-Liang Lin | 2016-07-05 |
| 9323155 | Double patterning strategy for contact hole and trench in photolithography | Hsiao-Wei Yeh, Chih-An Lin, Chien-Wei Wang, Feng-Cheng Hsu | 2016-04-26 |
| 9307614 | Color temperature and illumination adjusting system, and method thereof | Feng-Ling Lin, Hui-Ying Chen, Po-Shen Chen, Yuan-Ching Chen | 2016-04-05 |
| 9281273 | Designed-based interconnect structure in semiconductor structure | Chih-Liang Chen, Chih-Ming Lai, Yung-Sung Yen, Kam-Tou Sio, Tsong-Hua Ou +3 more | 2016-03-08 |
| 9214347 | Overlay mark assistant feature | Hsin-Chieh Yao, Hsien-Cheng Wang, Huang Chien Kai | 2015-12-15 |