MN

Munir D. Naeem

IBM: 22 patents #4,909 of 70,183Top 7%
Infineon Technologies Ag: 5 patents #1,696 of 7,486Top 25%
KT Kabushiki Kaisha Toshiba: 2 patents #9,982 of 21,451Top 50%
SA Siemens Aktiengesellschaft: 2 patents #6,658 of 22,248Top 30%
Overall (All Time): #185,471 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8772850 Embedded DRAM memory cell with additional patterning layer for improved strap formation Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim 2014-07-08
8492821 Enhanced capacitance trench capacitor Kangguo Cheng, Byeong Y. Kim, James P. Norum 2013-07-23
8426268 Embedded DRAM memory cell with additional patterning layer for improved strap formation Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim 2013-04-23
8227311 Method of forming enhanced capacitance trench capacitor Kangguo Cheng, Byeong Y. Kim, James P. Norum 2012-07-24
8003488 Shallow trench isolation structure compatible with SOI embedded DRAM Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim 2011-08-23
7871893 Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Christopher D. Sheraw, Richard S. Wise 2011-01-18
7592245 Poly filled substrate contact on SOI structure David M. Dobuzinsky, Byeong Y. Kim, Effendi Leobandung, Brian L. Tessier 2009-09-22
7393738 Subground rule STI fill for hot structure Byeong Y. Kim, Frank D. Tamweber, Xiaomeng Chen 2008-07-01
7358172 Poly filled substrate contact on SOI structure David M. Dobuzinsky, Byeong Y. Kim, Effendi Leobandung, Brian L. Tessier 2008-04-15
6893938 STI formation for vertical and planar transistors Hiroyuki Akatsu, Byeong Y. Kim, Rolf Weis, David Mark Dobuzinksy, Johnathan E. Faltermeier 2005-05-17
6890815 Reduced cap layer erosion for borderless contacts Johnathan E. Faltermeier, Jeremy K. Stephens, David M. Dobuzinsky, Larry Clevenger, Chienfan Yu +3 more 2005-05-10
6821900 Method for dry etching deep trenches in a substrate Satish D. Athavale, Rajiv Ranade, Gangadhara S. Mathad 2004-11-23
6733602 Polycrystalline material with surface features projecting from a surface thereof Lawrence A. Clevenger 2004-05-11
6566219 Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening Gerhard Kunkel, Shahid Butt, Ramachandra Divakaruni, Armin Reith 2003-05-20
6555204 Method of preventing bridging between polycrystalline micro-scale features Lawrence A. Clevenger 2003-04-29
6551942 Methods for etching tungsten stack structures — 2003-04-22
6544838 Method of deep trench formation with improved profile control and surface area Rajiv Ranade, Gangadhara S. Mathad 2003-04-08
6464806 Method of forming extruded structures from polycrystalline materials and devices formed thereby Lawrence A. Clevenger 2002-10-15
6359325 Method of forming nano-scale structures from polycrystalline materials and nano-scale structures formed thereby Lawrence A. Clevenger 2002-03-19
6284666 Method of reducing RIE lag for deep trench silicon etching Gangadhara S. Mathad, Byeong Y. Kim, Stephan Kudelka, Brian Lee, Heon Lee +3 more 2001-09-04
6002136 Microscope specimen holder and grid arrangement for in-situ and ex-situ repeated analysis — 1999-12-14
5976986 Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching Stuart M. Burns, Rosemary Christie, Virinder Grewal, Walter W. Kocon, Masaki Narita +2 more 1999-11-02
5846884 Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing Stuart M. Burns, Nancy Anne Greco, STEVE GRECO, Virinder Grewal, Ernest N. Levine +2 more 1998-12-08