GG

Gunter Grasshoff

Globalfoundries: 10 patents #365 of 4,424Top 9%
AM AMD: 9 patents #1,329 of 9,279Top 15%
GU Globalfoundries U.S.: 1 patents #344 of 665Top 55%
Overall (All Time): #221,283 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11031406 Semiconductor devices having silicon/germanium active regions with different germanium concentrations Elliot John Smith, Carsten Peters 2021-06-08
10522555 Semiconductor devices including Si/Ge active regions with different Ge concentrations Elliot John Smith, Carsten Peters 2019-12-31
10224251 Semiconductor devices and manufacturing techniques for reduced aspect ratio of neighboring gate electrode lines Hans-Peter Moll, Peter Baars 2019-03-05
10199479 Methods of forming a gate cap layer above a replacement gate structure Catherine B. Labelle 2019-02-05
10103067 Semiconductor device comprising trench isolation Peter Baars, Rico Hueselitz 2018-10-16
9412600 Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor Ralf van Bentum 2016-08-09
8932930 Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure Sven Beyer, Frank Seliger 2015-01-13
8791017 Methods of forming conductive structures using a spacer erosion technique 2014-07-29
8329549 Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure Sven Beyer, Frank Seliger 2012-12-11
8198166 Using high-k dielectrics as highly selective etch stop materials in semiconductor devices Thorsten Kammler, Ralf Richter, Markus Lenski 2012-06-12
8133814 Etch methods for semiconductor device fabrication Steffen Laufer 2012-03-13
8021942 Method of forming CMOS device having gate insulation layers of different type and thickness Andy Wei, Andrew Waite, Martin Trentzsch, Johannes Groschopf, Andreas Ott 2011-09-20
7723174 CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor Andrew Waite, Andy Wei 2010-05-25
7381622 Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process Andreas Hellmich, Fernando Luiz Koch, Andy Wei, Thorsten Kammler 2008-06-03
7005305 Signal layer for generating characteristic optical plasma emissions Christoph Schwan, Matthias Schaller 2006-02-28
6969676 Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process Christoph Schwan, Volker Grimm 2005-11-29
6879871 Advanced process control for a manufacturing process of a plurality of products with minimized control degradation after re-initialization upon occurrence of reset events Jan Raebiger, Andre Holfeld 2005-04-12
6875676 Methods for producing a highly doped electrode for a field effect transistor Karsten Wieczorek, Falk Graetsch 2005-04-05
6838010 System and method for wafer-based controlled patterning of features with critical dimensions Carsten Hartig 2005-01-04
6724096 Die corner alignment structure Thomas Werner, Bernd Schulz, Carsten Hartig 2004-04-20