Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907685 | Structure and method for random code generation | Judson R. Holt, Julien Frougier, Ryan Sporer, George R. Mulfinger | 2024-02-20 |
| 11056398 | Forming interconnect without gate cut isolation blocking opening formation | Naved Siddiqui, Shimpei Yamaguchi, Shreesh Narasimha | 2021-07-06 |
| 10991796 | Source/drain contact depth control | Lin Hu, Veeraraghavan S. Basker, Brian J. Greene, Kai Zhao, Keith H. Tabakman +1 more | 2021-04-27 |
| 10971625 | Epitaxial structures of a semiconductor device having a wide gate pitch | Michael V. Aquilino, Man Gu, Bradley Morgenfeld, Haiting Wang, KAVYA SREE DUGGIMPUDI +1 more | 2021-04-06 |
| 10930549 | Cap structure | Jinsheng Gao, Chih-Chiang Chang, Michael V. Aquilino, Patrick Carpenter, Junsic Hong +3 more | 2021-02-23 |
| 10833160 | Field-effect transistors with self-aligned and non-self-aligned contact openings | Michael V. Aquilino, Naved Siddiqui, Jessica Dechene, Daniel James Dechene, Shreesh Narasimha +1 more | 2020-11-10 |
| 10755982 | Methods of forming gate structures for transistor devices on an IC product | Abu Naser Zainuddin, Wei-Yuan MA, Joseph Versaggi, Jae Gon Lee, Thomas Kauerauf | 2020-08-25 |
| 10714376 | Method of forming semiconductor material in trenches having different widths, and related structures | Chih-Chiang Chang, Haifeng Sheng, Jiehui Shu, Haigou Huang, Pei Liu +2 more | 2020-07-14 |
| 10644156 | Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices | Jinsheng Gao, Michael V. Aquilino, Patrick Carpenter, Xusheng Wu, Haigou Huang | 2020-05-05 |
| 10522639 | Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device | Hui Zang, Haigou Huang, Veeraraghavan S. Basker, Christopher Nassar, Jinsheng Gao +1 more | 2019-12-31 |
| 10460986 | Cap structure | Jinsheng Gao, Chih-Chiang Chang, Michael V. Aquilino, Patrick Carpenter, Junsic Hong +3 more | 2019-10-29 |
| 10418455 | Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device | Hui Zang, Haigou Huang, Veeraraghavan S. Basker, Christopher Nassar, Jinsheng Gao +1 more | 2019-09-17 |
| 10388562 | Composite contact etch stop layer | Haigou Huang, Xusheng Wu, Jinsheng Gao | 2019-08-20 |
| 10373875 | Contacts formed with self-aligned cuts | Ruilong Xie, Chanro Park, Laertis Economikos, Haiting Wang, Hui Zang | 2019-08-06 |
| 10340142 | Methods, apparatus and system for self-aligned metal hard masks | Jinsheng Gao, Michael V. Aquilino, Patrick Carpenter, Jiehui Shu, Pei Liu +1 more | 2019-07-02 |
| 10325819 | Methods, apparatus and system for providing a pre-RMG replacement metal contact for a finFET device | Jinsheng Gao, Michael V. Aquilino, Patrick Carpenter, Jessica Dechene, Huy Cao +2 more | 2019-06-18 |
| 10269654 | Methods, apparatus and system for replacement contact for a finFET device | Jinsheng Gao, Michael V. Aquilino, Patrick Carpenter, Jessica Dechene, Huy Cao +2 more | 2019-04-23 |
| 10249616 | Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices | Hui Zang, Manfred Eller, Haiting Wang | 2019-04-02 |
| 10204797 | Methods, apparatus, and system for reducing step height difference in semiconductor devices | Jinsheng Gao, Michael V. Aquilino, Patrick Carpenter, Junsic Hong, Jessica Dechene +1 more | 2019-02-12 |
| 10062612 | Method and system for constructing FINFET devices having a super steep retrograde well | David Paul Brunco | 2018-08-28 |
| 9853116 | Partial sacrificial dummy gate with CMOS device with high-k metal gate | Dechao Guo, Wilfried E. Haensch, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong | 2017-12-26 |
| 9780002 | Threshold voltage and well implantation method for semiconductor devices | Xintuo Dai, Brian J. Greene, Mahender Kumar, Daniel James Dechene | 2017-10-03 |
| 9761452 | Devices and methods of forming SADP on SRAM and SAQP on logic | Jiehui Shu, Garo Derderian, Haifeng Sheng, Jinping Liu | 2017-09-12 |
| 9711624 | Methods for direct measurement of pitch-walking in lithographic multiple patterning | Fang Fang | 2017-07-18 |
| 9589829 | FinFET device including silicon oxycarbon isolation structure | Huy Cao, Guillaume Bouche | 2017-03-07 |