Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11908691 | Techniques to engineer nanoscale patterned features using ions | Simon Ruffell, John Hautala, Huixiong Dai | 2024-02-20 |
| 11699753 | LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods | Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, John Xia, Chi Nung Ni +1 more | 2023-07-11 |
| 11488823 | Techniques to engineer nanoscale patterned features using ions | Simon Ruffell, John Hautala, Huixiong Dai | 2022-11-01 |
| 11316044 | LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods | Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, John Xia, Chi Nung Ni +1 more | 2022-04-26 |
| 11043380 | Techniques to engineer nanoscale patterned features using ions | Simon Ruffell, John Hautala, Huixiong Dai | 2021-06-22 |
| 10971368 | Techniques for processing substrates using directional reactive ion etching | Steven R. Sherman, Simon Ruffell, John Hautala | 2021-04-06 |
| 10622452 | Transistors with dual gate conductors, and associated methods | Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, John Xia, Rajwinder Singh +2 more | 2020-04-14 |
| 10573744 | Self-aligned, dual-gate LDMOS transistors and associated methods | Marco A. Zuniga, Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh | 2020-02-25 |
| 10134585 | Low temperature atomic layer deposition of oxides on compound semiconductors | Kasra Sardashti, Tobin Kaufman-Osborn, Tyler Kent, Andrew C. Kummel, Shariq Siddiqui +2 more | 2018-11-20 |
| 10109534 | Multi-threshold voltage (Vt) workfunction metal by selective atomic layer deposition (ALD) | Naomi Yoshida, Seshadri Ganguli, David Thompson, Mei Chang | 2018-10-23 |
| 10008384 | Techniques to engineer nanoscale patterned features using ions | Simon Ruffell, John Hautala, Huixiong Dai | 2018-06-26 |
| 9934981 | Techniques for processing substrates using directional reactive ion etching | Steven R. Sherman, Simon Ruffell, John Hautala | 2018-04-03 |
| 9673277 | Methods and apparatus for forming horizontal gate all around device structures | Bingxi Wood, Naomi Yoshida, Lin Dong, Shiyu Sun, Chi Nung Ni +1 more | 2017-06-06 |
| 9378941 | Interface treatment of semiconductor surfaces with high density low energy plasma | Aneesh Nainani, Bhushan Zope, Leonid Dorf, Shahid Rauf, Mathew Abraham +1 more | 2016-06-28 |
| 9337314 | Technique for selectively processing three dimensional device | Nilay A. Pradhan, Benjamin Colombeau, Naushad K. Variam, Mandar B. Pandit, Christopher Dennis Bencher | 2016-05-10 |
| 9190498 | Technique for forming a FinFET device using selective ion implantation | Srinivas D. Nemani, John Hautala, Ludovic Godet, Yuri Erokhin | 2015-11-17 |
| 9018054 | Metal gate structures for field effect transistors and method of fabrication | Naomi Yoshida | 2015-04-28 |
| 8999829 | Dual gate process | Bingxi Wood | 2015-04-07 |
| 8999821 | Fin formation by epitaxial deposition | Bingxi Wood, Errol Antonio C. Sanchez, Yihwan Kim, Yi-Chiau Huang, John Boland | 2015-04-07 |
| 8864915 | Cleaning methods for improved photovoltaic module efficiency | Renhe Jia, Liming Zhang, Dapeng Wang, Tzay-Fa Su, Vijay Parihar | 2014-10-21 |
| 6388475 | Voltage tolerant high drive pull-up driver for an I/O buffer | Lawrence T. Clark | 2002-05-14 |
| 6287908 | Transistor device configurations for high voltage applications and improved device performance | — | 2001-09-11 |
| 6172401 | Transistor device configurations for high voltage applications and improved device performance | — | 2001-01-09 |