Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11699753 | LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods | Tom K. Castro, Rajwinder Singh, Adam Brand, John Xia, Chi Nung Ni +1 more | 2023-07-11 |
| 11557588 | Multi-transistor device including first and second LDMOS transistors having respective drift regions separated in a thickness direction by a shared RESURF layer | Vipindas Pala, Vijay Parthasarathy, Marco A. Zuniga, John Xia | 2023-01-17 |
| 11316044 | LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods | Tom K. Castro, Rajwinder Singh, Adam Brand, John Xia, Chi Nung Ni +1 more | 2022-04-26 |
| 10964694 | Multi-transistor device including first and second LDMOS transistors having respective drift regions separated in a thickness direction by a shared RESURF layer | Vipindas Pala, Vijay Parthasarathy, Marco A. Zuniga, John Xia | 2021-03-30 |
| 10833164 | LDMOS transistors and associated systems and methods | John Xia, Marco A. Zuniga, Vijay Parthasarathy | 2020-11-10 |
| 10622452 | Transistors with dual gate conductors, and associated methods | Tom K. Castro, Marco A. Zuniga, Adam Brand, John Xia, Rajwinder Singh +2 more | 2020-04-14 |
| 10573744 | Self-aligned, dual-gate LDMOS transistors and associated methods | Marco A. Zuniga, Adam Brand, Tom K. Castro, Rajwinder Singh | 2020-02-25 |
| 10284072 | Voltage regulators with multiple transistors | Marco A. Zuniga, Chiteh Chiang, Yang Lu, Amit Paul, Jun Ruan +1 more | 2019-05-07 |
| 10269916 | LDMOS transistors and associated systems and methods | John Xia, Marco A. Zuniga, Vijay Parthasarathy | 2019-04-23 |
| 10229993 | LDMOS transistors including resurf layers and stepped-gates, and associated systems and methods | John Xia, Marco A. Zungia | 2019-03-12 |
| 10199475 | LDMOS transistors and associated systems and methods | John Xia, Marco A. Zuniga, Vijay Parthasarathy | 2019-02-05 |
| 10147801 | Transistor with buried P+ and source contact | Marco A. Zuniga, Yang Lu, Jayasimha Prasad, Amit Paul, Jun Ruan | 2018-12-04 |
| 9722483 | Voltage regulators with multiple transistors | Marco A. Zuniga, Chiteh Chiang, Yang Lu, Amit Paul, Jun Ruan +1 more | 2017-08-01 |
| 9159804 | Vertical gate LDMOS device | Marco A. Zuniga, Yang Lu, Jayasimha Prasad, Amit Paul, Jun Ruan | 2015-10-13 |
| 8969158 | Vertical gate LDMOS device | Marco A. Zuniga, Yang Lu, Jayasimha Prasad, Amit Paul, Jun Ruan | 2015-03-03 |
| 8866217 | Vertical gate LDMOS device | Marco A. Zuniga, Yang Lu, Jayasimha Prasad, Amit Paul, Jun Ruan | 2014-10-21 |
| 8709899 | Vertical gate LDMOS device | Marco A. Zuniga, Yang Lu, Jayasimha Prasad, Amit Paul, Jun Ruan +1 more | 2014-04-29 |
| 8647950 | Vertical gate LDMOS device | Marco A. Zuniga, Yang Lu, Jayasimha Prasad, Amit Paul, Jun Ruan | 2014-02-11 |
| 7235827 | Vertical power JFET with low on-resistance for high voltage applications | Ali Salih | 2007-06-26 |
| 7049677 | Low cost dielectric isolation method for integration of vertical power MOSFET and lateral driver devices | Ali Salih | 2006-05-23 |
| 6872602 | Carrier coupler for thyristor-based semiconductor device | Farid Nemati, Andrew E. Horch, Scott Robins | 2005-03-29 |
| 6756612 | Carrier coupler for thyristor-based semiconductor device | Farid Nemati, Andrew E. Horch, Scott Robins | 2004-06-29 |
| 6242972 | Clamp circuit using PMOS-transistors with a weak temperature dependency | — | 2001-06-05 |