Issued Patents All Time
Showing 101–125 of 173 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10403752 | Prevention of subchannel leakage current in a semiconductor device with a fin structure | Karthik Jambunathan, Chandra S. Mohapatra, Anand S. Murthy, Stephen M. Cea, Tahir Ghani | 2019-09-03 |
| 10403626 | Fin sculpting and cladding during replacement gate process for transistor channel applications | Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi | 2019-09-03 |
| 10396201 | Methods of forming dislocation enhanced strain in NMOS structures | Michael Jackson, Anand S. Murthy, Saurabh Morarka, Chandra S. Mohapatra | 2019-08-27 |
| 10396203 | Pre-sculpting of Si fin elements prior to cladding for transistor channel applications | Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi | 2019-08-27 |
| 10373977 | Transistor fin formation via cladding on sacrificial core | Anand S. Murthy, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung +4 more | 2019-08-06 |
| 10304927 | Selective germanium p-contact metalization through trench | Anand S. Murthy, Tahir Ghani | 2019-05-28 |
| 10297670 | Contact resistance reduction employing germanium overlayer pre-contact metalization | Anand S. Murthy, Tahir Ghani | 2019-05-21 |
| 10290709 | Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces | Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani, Willy Rachmady, Gilbert Dewey +2 more | 2019-05-14 |
| 10243078 | Carrier confinement for high mobility channel devices | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +3 more | 2019-03-26 |
| 10229997 | Indium-rich NMOS transistor channels | Chandra S. Mohapatra, Anand S. Murthy, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros +3 more | 2019-03-12 |
| 10211208 | High-mobility semiconductor source/drain spacer | Gilbert Dewey, Matthew V. Metz, Anand S. Murthy, Tahir Ghani, Willy Rachmady +2 more | 2019-02-19 |
| 10153372 | High mobility strained channels for fin-based NMOS transistors | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Willy Rachmady +1 more | 2018-12-11 |
| 10147817 | Techniques for integration of Ge-rich p-MOS source/drain | Anand S. Murthy, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi | 2018-12-04 |
| 10141311 | Techniques for achieving multiple transistor fin dimensions on a single die | Anand S. Murthy | 2018-11-27 |
| 10109711 | CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel | Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Kelin J. Kuhn +1 more | 2018-10-23 |
| 10109628 | Transistor device with gate control layer undercutting the gate dielectric | Anand S. Murthy, Nick Lindert | 2018-10-23 |
| 10090383 | Column IV transistors for PMOS integration | Anand S. Murthy | 2018-10-02 |
| 10084043 | High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin | Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +4 more | 2018-09-25 |
| 10074573 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani +2 more | 2018-09-11 |
| 10014412 | Pre-sculpting of Si fin elements prior to cladding for transistor channel applications | Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi | 2018-07-03 |
| 9997414 | Ge/SiGe-channel and III-V-channel transistors on the same die | Anand S. Murthy, Karthik Jambunathan | 2018-06-12 |
| 9966440 | Tin doped III-V material contacts | Anand S. Murthy, Michael Jackson, Harold W. Kennel | 2018-05-08 |
| 9929273 | Apparatus and methods of forming fin structures with asymmetric profile | Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi +3 more | 2018-03-27 |
| 9893149 | High mobility strained channels for fin-based transistors | Stephen M. Cea, Anand S. Murthy, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros +1 more | 2018-02-13 |
| 9882009 | High resistance layer for III-V channel deposited on group IV substrates for MOS transistors | Anand S. Murthy | 2018-01-30 |