Issued Patents All Time
Showing 126–150 of 173 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9876113 | Method for improving transistor performance through reducing the salicide interface resistance | Anand S. Murthy, Boyan Boyanov, Thomas Hoffmann | 2018-01-23 |
| 9859424 | Techniques for integration of Ge-rich p-MOS source/drain contacts | Anand S. Murthy, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi | 2018-01-02 |
| 9842928 | Tensile source drain III-V transistors for mobility improved n-MOS | Anand S. Murthy, Chandra S. Mohapatra | 2017-12-12 |
| 9812524 | Nanowire transistor devices and forming techniques | Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine | 2017-11-07 |
| 9754940 | Self-aligned contact metallization for reduced contact resistance | Anand S. Murthy, Tahir Ghani | 2017-09-05 |
| 9728464 | Self-aligned 3-D epitaxial structures for MOS device fabrication | Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani | 2017-08-08 |
| 9722023 | Selective germanium P-contact metalization through trench | Anand S. Murthy, Tahir Ghani | 2017-08-01 |
| 9705000 | III-V layers for n-type and p-type MOS source-drain contacts | Anand S. Murthy, Tahir Ghani | 2017-07-11 |
| 9691843 | Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition | Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Van H. Le | 2017-06-27 |
| 9680016 | Method for improving transistor performance through reducing the salicide interface resistance | Anand S. Murthy, Boyan Boyanov, Thomas Hoffmann | 2017-06-13 |
| 9673302 | Conversion of strain-inducing buffer to electrical insulator | Annalisa Cappellani, Van H. Le, Kelin J. Kuhn, Stephen M. Cea | 2017-06-06 |
| 9653584 | Pre-sculpting of Si fin elements prior to cladding for transistor channel applications | Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi | 2017-05-16 |
| 9633835 | Transistor fabrication technique including sacrificial protective layer for source/drain at contact location | Anand S. Murthy, Michael Jackson, Michael L. Hattendorf, Subhash M. Joshi | 2017-04-25 |
| 9627384 | Transistors with high concentration of boron doped germanium | Anand S. Murthy, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros +3 more | 2017-04-18 |
| 9583491 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani +2 more | 2017-02-28 |
| 9559160 | Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition | Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Van H. Le | 2017-01-31 |
| 9484432 | Contact resistance reduction employing germanium overlayer pre-contact metalization | Anand S. Murthy, Tahir Ghani | 2016-11-01 |
| 9472613 | Conversion of strain-inducing buffer to electrical insulator | Annalisa Cappellani, Van H. Le, Kelin J. Kuhn, Stephen M. Cea | 2016-10-18 |
| 9437710 | Method for improving transistor performance through reducing the salicide interface resistance | Anand S. Murthy, Boyan Boyanov, Thomas Hoffman | 2016-09-06 |
| 9437691 | Column IV transistors for PMOS integration | Anand S. Murthy | 2016-09-06 |
| 9397102 | III-V layers for N-type and P-type MOS source-drain contacts | Anand S. Murthy, Tahir Ghani | 2016-07-19 |
| 9349810 | Selective germanium P-contact metalization through trench | Anand S. Murthy, Tahir Ghani | 2016-05-24 |
| 9343559 | Nanowire transistor devices and forming techniques | Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine | 2016-05-17 |
| 9224810 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani +2 more | 2015-12-29 |
| 9224735 | Self-aligned contact metallization for reduced contact resistance | Anand S. Murthy, Tahir Ghani | 2015-12-29 |