Issued Patents All Time
Showing 51–75 of 241 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11950407 | Memory architecture with shared bitline at back-end-of-line | Juan G. Alzate Vinasco, Travis W. Lajoie, Kimberly Pierce, Elliot N. Tan, Yu-Jin Chen +3 more | 2024-04-02 |
| 11923371 | Voltage regulator circuit including one or more thin-film transistors | Van H. Le, Seung Hoon Sung, Ravi Pillarisetty, Marko Radosavljevic | 2024-03-05 |
| 11901404 | Capacitor architectures in semiconductor devices | Sudipto Naskar, Manish Chandhok, Roman Caudillo, Scott B. Clendenning, Cheyun Lin | 2024-02-13 |
| 11895846 | Double-gated ferroelectric field-effect transistor | Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov | 2024-02-06 |
| 11895824 | Vertical 1T-1C DRAM array | Ravi Pillarisetty, Van H. Le, Gilbert Dewey | 2024-02-06 |
| 11888034 | Transistors with metal chalcogenide channel materials | Ashish Agarwal, Urusa Alaan, Christopher J. Jezewski, Kevin Lin, Carl Naylor | 2024-01-30 |
| 11881517 | Channel structures for thin-film transistors | Cory E. Weber, Van H. Le, Sean T. Ma | 2024-01-23 |
| 11862728 | Dual gate control for trench shaped thin film transistors | Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung +2 more | 2024-01-02 |
| 11862730 | Top-gate doped thin film transistor | Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey | 2024-01-02 |
| 11862729 | Vertical multi-gate thin film transistors | Yih Wang, Sean T. Ma, Van H. Le | 2024-01-02 |
| 11849572 | 3D 1T1C stacked DRAM structure and method to fabricate | Aaron D. Lilak, Sean T. Ma | 2023-12-19 |
| 11843054 | Vertical architecture of thin film transistors | Van H. Le, Seung Hoon Sung, Benjamin Chu-Kung, Miriam Reshotko, Matthew V. Metz +6 more | 2023-12-12 |
| 11843058 | Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures | Gilbert Dewey, Van H. Le, Jack T. Kavalieros, Shriram Shivaraman, Seung Hoon Sung +4 more | 2023-12-12 |
| 11837648 | Stacked thin film transistors with nanowires | Seung Hoon Sung, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani | 2023-12-05 |
| 11830788 | Integrated circuits and methods for forming integrated circuits | Carl Naylor, Ashish Agrawal, Urusa Alaan, Christopher J. Jezewski, Mauro J. Kobrinsky +1 more | 2023-11-28 |
| 11832438 | Capacitor connections in dielectric layers | Travis W. Lajoie, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros +13 more | 2023-11-28 |
| 11817442 | Hybrid manufacturing for integrated circuit devices and assemblies | Wilfred Gomes, Mauro J. Kobrinsky, Doug B. Ingerly | 2023-11-14 |
| 11812599 | Compute near memory with backend memory | Noriyuki Sato, Sarah Atanasov, Huseyin Ekin Sumbul, Gregory K. Chen, Phil Knag +3 more | 2023-11-07 |
| 11812600 | Vertical memory cell with self-aligned thin film transistor | Seung Hoon Sung, Charles C. Kuo, Van H. Le, Jack T. Kavalieros | 2023-11-07 |
| 11791375 | Capacitor architectures in semiconductor devices | Sudipto Naskar, Manish Chandhok, Roman Caudillo, Scott B. Clendenning, Cheyun Lin | 2023-10-17 |
| 11784251 | Transistors with ferroelectric spacer and methods of fabrication | Seung Hoon Sung, Gilbert Dewey, Van H. Le, Jack T. Kavalieros | 2023-10-10 |
| 11777013 | Channel formation for three dimensional transistors | Willy Rachmady, Van H. Le, Jack T. Kavalieros, Gilbert Dewey, Matthew V. Metz | 2023-10-03 |
| 11777029 | Vertical transistors for ultra-dense logic and memory applications | Nazila Haratipour, I-Cheng Tung, Arnab Sen Gupta, Van H. Le, Matthew V. Metz +2 more | 2023-10-03 |
| 11764303 | Thin film transistors having double gates | Van H. Le, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey | 2023-09-19 |
| 11764306 | Multi-layer crystalline back gated thin film transistor | Van H. Le, Gilbert Dewey, Kent Millard, Jack T. Kavalieros, Shriram Shivaraman +6 more | 2023-09-19 |