Issued Patents All Time
Showing 151–175 of 293 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7098083 | High impedance antifuse | John A. Fifield, Russell J. Houghton | 2006-08-29 |
| 7087499 | Integrated antifuse structure for FINFET and CMOS devices | Jed H. Rankin, Wagdi W. Abadeer, Jeffrey S. Brown | 2006-08-08 |
| 7087948 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Jack A. Mandelman, Carl Radens, Richard Strub | 2006-08-08 |
| 7078259 | Method for integrating thermistor | Jon A. Casey, William J. Ferrante, Edward W. Kiewra, Carl Radens | 2006-07-18 |
| 7064410 | MOS antifuse with low post-program resistance | Carl Radens | 2006-06-20 |
| 7061308 | Voltage divider for integrated circuits | Wagdi W. Abadeer, John A. Fifield | 2006-06-13 |
| 7026202 | Inverse-T gate structure using damascene processing | Jack A. Mandelman, Carl Radens | 2006-04-11 |
| 7015552 | Dual work function semiconductor structure with borderless contact and method of fabricating the same | Qiuyi Ye, Yujun Li | 2006-03-21 |
| 6982591 | Method and circuit for compensating for tunneling current | Wagdi W. Abadeer, Jennifer E. Appleyard, John A. Fifield | 2006-01-03 |
| 6972220 | Structures and methods of anti-fuse formation in SOI | Claude L. Bertin, Ramachandra Divakaruni, Russell J. Houghton, Jack A. Mandelman | 2005-12-06 |
| 6943452 | Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality | Claude L. Bertin, Gordon A. Kelley, Jr., Dennis Arthur Schmidt, Jerzy M. Zalesinski | 2005-09-13 |
| 6940149 | Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base | Rama Divakaruni, Gregory G. Freeman, Marwan H. Khater | 2005-09-06 |
| 6908815 | Dual work function semiconductor structure with borderless contact and method of fabricating the same | Qiuyi Ye, Yujun Li | 2005-06-21 |
| 6882027 | Methods and apparatus for providing an antifuse function | Axel Brintzinger, Carl Radens | 2005-04-19 |
| 6879638 | Method and apparatus for providing communication between electronic devices | Claude L. Bertin, Anthony R. Bonaccio, John A. Fifield, Wilbur D. Pricer | 2005-04-12 |
| 6879021 | Electronically programmable antifuse and circuits made therewith | John A. Fitfield, Wagdi W. Abadeer | 2005-04-12 |
| 6876035 | High voltage N-LDMOS transistors having shallow trench isolation region | Wagdi W. Abadeer, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jed H. Rankin | 2005-04-05 |
| 6869846 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Jack A. Mandelman, Carl Radens, Richard Strub | 2005-03-22 |
| 6844609 | Antifuse with electrostatic assist | William T. Motsiff, Richard Q. Williams | 2005-01-18 |
| 6818487 | Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof | Louis L. Hsu, Jack A. Mandelman, Li-Kong Wang | 2004-11-16 |
| 6812122 | Method for forming a voltage programming element | Claude L. Bertin, Erik L. Hedberg, Russell J. Houghton, Max G. Levy, Rick L. Mohler +1 more | 2004-11-02 |
| 6802033 | Low-power critical error rate communications controller | Claude L. Bertin, Alvar A. Dean, Kenneth J. Goodnow, Scott Whitney Gould, Patrick E. Perry +1 more | 2004-10-05 |
| 6794726 | MOS antifuse with low post-program resistance | Carl Radens | 2004-09-21 |
| 6790722 | Logic SOI structure, process and application for vertical bipolar transistor | Ramachandra Divakaruni, Russell J. Houghton, Jack A. Mandelman, Wilbur D. Pricer | 2004-09-14 |
| 6770907 | Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure | Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna +2 more | 2004-08-03 |