WT

William R. Tonti

IBM: 290 patents #77 of 70,183Top 1%
Infineon Technologies Ag: 3 patents #2,452 of 7,486Top 35%
SA Siemens Aktiengesellschaft: 2 patents #6,658 of 22,248Top 30%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
📍 South Burlington, VT: #2 of 1,136 inventorsTop 1%
🗺 Vermont: #6 of 4,968 inventorsTop 1%
Overall (All Time): #1,380 of 4,157,543Top 1%
293
Patents All Time

Issued Patents All Time

Showing 101–125 of 293 patents

Patent #TitleCo-InventorsDate
7521776 Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers Ethan H. Cannon, Toshiharu Furukawa, Charles W. Koburger, III, Jack A. Mandelman 2009-04-21
7494916 Design structures incorporating interconnect structures with liner repair layers Louis L. Hsu, Jack A. Mandelman, Chih-Chao Yang 2009-02-24
7491618 Methods and semiconductor structures for latch-up suppression using a conductive region Toshiharu Furukawa, David V. Horak, Charles W. Koburger, III, Jack A. Mandelman 2009-02-17
7477541 Memory elements and methods of using the same Wagdi W. Abadeer, Anthony R. Bonaccio, Jack A. Mandelman, Sebastian T. Ventrone 2009-01-13
7473904 Device for monitoring ionizing radiation in silicon-on insulator integrated circuits Wagdi W. Abadeer, Ethan H. Cannon, Dennis Thomas Cox 2009-01-06
7473985 Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates Louis L. Hsu, Jack A. Mandelman 2009-01-06
7473970 Concurrent fin-fet and thick body device fabrication Wagdi W. Abadeer, Jeffrey S. Brown, David M. Fried, Robert J. Gauthier, Jr., Edward J. Nowak +1 more 2009-01-06
7472320 Autonomous self-monitoring and corrective operation of an integrated circuit Zachary E. Berndlmaier, Stephen F. Geissler 2008-12-30
7462547 Method of fabricating a bipolar transistor having reduced collector-base capacitance Hiroyuki Akatsu, Rama Divakaruni, Marwan H. Khater, Christopher M. Schnabel 2008-12-09
7460003 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer Louis L. Hsu, Jack A. Mandelman, Chih-Chao Yang 2008-12-02
7442583 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable Anthony R. Bonaccio, Karl R. Erickson, John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone 2008-10-28
7425754 Structure and method of self-aligned bipolar transistor having tapered collector Hiroyuki Akatsu, Rama Divakaruni, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater 2008-09-16
7417300 Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof Roger A. Booth, Jr., Jack A. Mandelman 2008-08-26
7396762 Interconnect structures with linear repair layers and methods for forming such interconnection structures Louis L. Hsu, Jack A. Mandelman, Chih-Chao Yang 2008-07-08
7394268 Carrier for test, burn-in, and first level packaging Claude L. Bertin, Wayne F. Ellis, Mark W. Kellogg, Jerzy M. Zalesinski, James M. Leas +1 more 2008-07-01
7382036 Doped single crystal silicon silicided eFuse Edward J. Nowak, Jed H. Rankin, Richard Q. Williams 2008-06-03
7381610 Semiconductor transistors with contact holes close to gates Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III 2008-06-03
7381594 CMOS compatible shallow-trench efuse structure and method Louis L. Hsu, Jack A. Mandelman, Chih-Chao Yang 2008-06-03
7375339 Monitoring ionizing radiation in silicon-on insulator integrated circuits Wagdi W. Abadeer, Ethan H. Cannon, Dennis Thomas Cox 2008-05-20
7358823 Programmable capacitors and methods of using the same Wagdi W. Abadeer, Anthony R. Bonaccio, Jack A. Mandelman, Sebastian T. Ventrone 2008-04-15
7358164 Crystal imprinting methods for fabricating substrates with thin active silicon layers Louis L. Hsu, Jack A. Mandelman 2008-04-15
7352034 Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Roger A. Booth, Jr., Jack A. Mandelman 2008-04-01
7348280 Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions Louis L. Hsu, Jack A. Mandelman, Chih-Chao Yang 2008-03-25
7336095 Changing chip function based on fuse states Karl R. Erickson, John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone 2008-02-26
7301210 Method and structure to process thick and thin fins and variable fin to fin spacing Wagdi W. Abadeer, Jeffrey S. Brown, Kiran V. Chatty, Robert J. Gauthier, Jr., Jed H. Rankin 2007-11-27