Issued Patents All Time
Showing 126–150 of 223 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8896067 | Method of forming finFET of variable channel width | Marc A. Bergendahl, David V. Horak, Chih-Chao Yang, Charles W. Koburger, III | 2014-11-25 |
| 8883623 | Facilitating gate height uniformity and inter-layer dielectric protection | Ruilong Xie, Xiuyu Cai, Pranatharthiharan Haran Balasubramanian | 2014-11-11 |
| 8877645 | Integrated circuit structure having selectively formed metal cap | Chih-Chao Yang, David V. Horak, Charles W. Koburger, III | 2014-11-04 |
| 8871624 | Sealed air gap for semiconductor chip | David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Douglas C. La Tulipe, Jr. | 2014-10-28 |
| 8859379 | Stress enhanced finFET devices | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2014-10-14 |
| 8853076 | Self-aligned contacts | Su Chen Fan, David V. Horak, David L. Rath, Muthumanickam Sankarapandian | 2014-10-07 |
| 8836031 | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices | Balasubramanian S. Haran, David V. Horak, Charles W. Koburger, III | 2014-09-16 |
| 8835305 | Method of fabricating a profile control in interconnect structures | Chih-Chao Yang, Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak +4 more | 2014-09-16 |
| 8835244 | Integrated circuits and methods for fabricating integrated circuits having metal gate electrodes | Ruilong Xie, Chanro Park | 2014-09-16 |
| 8829617 | Uniform finFET gate height | Balasubramanian S. Haran, Sanjay C. Mehta, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert | 2014-09-09 |
| 8828876 | Dual mandrel sidewall image transfer processes | David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-09-09 |
| 8828862 | Air-dielectric for subtractive etch line and via metallization | David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Chih-Chao Yang | 2014-09-09 |
| 8828828 | MOSFET including asymmetric source and drain regions | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2014-09-09 |
| 8809920 | Prevention of fin erosion for semiconductor devices | Ali Khakifirooz, Thomas N. Adam, Kangguo Cheng, Alexander Reznicek, Raghavasimhan Sreenivasan +2 more | 2014-08-19 |
| 8809183 | Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer | Griselda Bonilla, Lawrence A. Clevenger, Elbert E. Huang, Satyanarayana V. Nitta | 2014-08-19 |
| 8802558 | Copper interconnect structures and methods of making same | Chih-Chao Yang, Marc A. Bergendahl, David V. Horak, Baozhen Li | 2014-08-12 |
| 8803318 | Semiconductor chips including passivation layer trench structure | Deepak Kulkarni, Michael Lane, Satyanayana V. Nitta | 2014-08-12 |
| 8803321 | Dual damascene dual alignment interconnect scheme | Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-08-12 |
| 8796783 | Borderless contact structure employing dual etch stop layers | Su Chen Fan, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-08-05 |
| 8785284 | FinFETs and fin isolation structures | Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-07-22 |
| 8772933 | Interconnect structure and method of making same | Ya Ou, Terry A. Spooner | 2014-07-08 |
| 8772874 | MOSFET including asymmetric source and drain regions | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2014-07-08 |
| 8772180 | Interconnect structure and method of making same | Ya Ou, Terry A. Spooner | 2014-07-08 |
| 8765585 | Method of forming a borderless contact structure employing dual etch stop layers | Su Chen Fan, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-07-01 |
| 8754520 | Formation of air gap with protection of metal lines | Takeshi Nogami, Shyng-Tsong Chen, David V. Horak, Son V. Nguyen, Chih-Chao Yang | 2014-06-17 |