Issued Patents All Time
Showing 151–175 of 223 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8754483 | Low-profile local interconnect and method of making the same | David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-06-17 |
| 8735279 | Air-dielectric for subtractive etch line and via metallization | David V. Horak, Elbert E. Huang, Charles W. Koburger, III, Chih-Chao Yang | 2014-05-27 |
| 8716127 | Metal alloy cap integration | Chih-Chao Yang, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, III | 2014-05-06 |
| 8704343 | Borderless interconnect line structure self-aligned to upper and lower level contact vias | David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-04-22 |
| 8703604 | Creation of vias and trenches with different depths | David V. Horak, Takeshi Nogami, Chih-Chao Yang | 2014-04-22 |
| 8703553 | MOS capacitors with a finFET process | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2014-04-22 |
| 8703550 | Dual shallow trench isolation liner for preventing electrical shorts | Bruce B. Doris, Prasanna Khare, Qing Liu, Nicolas Loubet, Maud Vinet | 2014-04-22 |
| 8673738 | Shallow trench isolation structures | Bruce B. Doris, Kangguo Cheng, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kulkarni +1 more | 2014-03-18 |
| 8637400 | Interconnect structures and methods for back end of the line integration | David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2014-01-28 |
| 8637381 | High-k dielectric and silicon nitride box region | Effendi Leobandung, Dae-Gyu Park, Zhibin Ren, Ghavam G. Shahidi, Leathen Shi | 2014-01-28 |
| 8629511 | Mask free protection of work function material portions in wide replacement gate electrodes | Charles W. Koburger, III, Marc A. Bergendahl, David V. Horak, Chih-Chao Yang | 2014-01-14 |
| 8629008 | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices | Balasubramanian S. Haran, David V. Horak, Charles W. Koburger, III | 2014-01-14 |
| 8623712 | Bulk fin-field effect transistors with well defined isolation | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2014-01-07 |
| 8609534 | Electrical fuse structure and method of fabricating same | Chih-Chao Yang, David V. Horak, Charles W. Koburger, III | 2013-12-17 |
| 8604539 | Bulk fin-field effect transistors with well defined isolation | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2013-12-10 |
| 8592290 | Cut-very-last dual-EPI flow | Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S. Haran, Nicolas Loubet +3 more | 2013-11-26 |
| 8592263 | FinFET diode with increased junction area | Theodorus E. Standaert, Kangguo Cheng, Balasubramanian S. Haran, Tenko Yamashita | 2013-11-26 |
| 8581320 | MOS capacitors with a finfet process | Kangguo Cheng, Balasubramanian S. Haran, Theodorus E. Standaert, Tenko Yamashita | 2013-11-12 |
| 8569168 | Dual-metal self-aligned wires and vias | Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang | 2013-10-29 |
| 8569152 | Cut-very-last dual-epi flow | Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Balasubramanian S. Haran, Nicolas Loubet +3 more | 2013-10-29 |
| 8569125 | FinFET with improved gate planarity | Theodorus E. Standaert, Kangguo Cheng, Balasubramanian S. Haran, Soon-Cheon Seo, Tenko Yamashita | 2013-10-29 |
| 8558284 | Integrated circuit line with electromigration barriers | David V. Horak, Takeshi Nogami, Chih-Chao Yang | 2013-10-15 |
| 8525339 | Hybrid copper interconnect structure and method of fabricating same | Chih-Chao Yang, David V. Horak, Charles W. Koburger, III | 2013-09-03 |
| 8518773 | Method of fabricating semiconductor capacitor | David V. Horak, Hosadurga Shobha, Chih-Chao Yang | 2013-08-27 |
| 8492265 | Pad bonding employing a self-aligned plated liner for adhesion enhancement | Chih-Chao Yang, David V. Horak, Takeshi Nogami | 2013-07-23 |