Issued Patents All Time
Showing 101–125 of 165 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818741 | Structure and method to prevent EPI short between trenches in FINFET eDRAM | Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz +5 more | 2017-11-14 |
| 9818054 | Tag with tunable retro-reflectors | Evan G. Colgan, Fuad E. Doany, Li-Wen Hung, Bucknell C. Webb | 2017-11-14 |
| 9761727 | Vertical FETs with variable bottom spacer recess | Hari V. Mallela, Rajasekhar Venigalla | 2017-09-12 |
| 9741722 | Dummy gate structure for electrical isolation of a fin DRAM | John E. Barth, Jr., Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz +4 more | 2017-08-22 |
| 9735275 | Channel replacement and bimodal doping scheme for bulk finFET threshold voltage modulation with reduced performance penalty | Gauri Karve, Robert R. Robison | 2017-08-15 |
| 9735162 | Dynamic random access memory cell with self-aligned strap | John E. Barth, Jr., Kangguo Cheng, Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran +1 more | 2017-08-15 |
| 9728466 | Vertical field effect transistors with metallic source/drain regions | Hari V. Mallela, Robert R. Robison, Rajasekhar Venigalla | 2017-08-08 |
| 9680019 | Fin-type field-effect transistors with strained channels | Henry K. Utomo, Yun-Yu Wang | 2017-06-13 |
| 9679993 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran | 2017-06-13 |
| 9647124 | Semiconductor devices with graphene nanoribbons | Emre Alptekin, Viraj Y. Sardesai | 2017-05-09 |
| 9601491 | Vertical field effect transistors having epitaxial fin channel with spacers below gate structure | Hari V. Mallela, Rajasekhar Venigalla | 2017-03-21 |
| 9601380 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran | 2017-03-21 |
| 9595527 | Coaxial carbon nanotube capacitor for eDRAM | — | 2017-03-14 |
| 9577068 | Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation | Gregory Costrini, Ravikumar Ramachandran, Richard S. Wise | 2017-02-21 |
| 9564445 | Dummy gate structure for electrical isolation of a fin DRAM | John E. Barth, Jr., Kangguo Cheng, Bruce B. Doris, Herbert L. Ho, Ali Khakifirooz +4 more | 2017-02-07 |
| 9564443 | Dynamic random access memory cell with self-aligned strap | John E. Barth, Jr., Kangguo Cheng, Herbert L. Ho, Ali Khakifirooz, Ravikumar Ramachandran +1 more | 2017-02-07 |
| 9536900 | Forming fins of different semiconductor materials on the same substrate | Ravikumar Ramachandran, Huiling Shang, Keith H. Tabakman, Henry K. Utomo | 2017-01-03 |
| 9530684 | Method and structure to suppress finFET heating | Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran | 2016-12-27 |
| 9530700 | Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch | Hari V. Mallela, Rajasekhar Venigalla | 2016-12-27 |
| 9514992 | Unidirectional spacer in trench silicide | Emre Alptekin, Sameer H. Jain, Unoh Kwon, Zhengwen Li, Hari V. Mallela +3 more | 2016-12-06 |
| 9515168 | Fin end spacer for preventing merger of raised active regions | Emre Alptekin, Sameer H. Jain, Viraj Y. Sardesai, Cung D. Tran | 2016-12-06 |
| 9496368 | Partial spacer for increasing self aligned contact process margins | Emre Alptekin, Ravikumar Ramachandran, Viraj Y. Sardesai | 2016-11-15 |
| 9496258 | Semiconductor fin isolation by a well trapping fin portion | Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Ravikumar Ramachandran, Huiling Shang | 2016-11-15 |
| 9466693 | Self aligned replacement metal source/drain finFET | Emre Alptekin, Robert R. Robison | 2016-10-11 |
| 9437503 | Vertical FETs with variable bottom spacer recess | Hari V. Mallela, Rajasekhar Venigalla | 2016-09-06 |