Issued Patents All Time
Showing 76–100 of 165 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10177154 | Structure and method to prevent EPI short between trenches in FinFET eDRAM | Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz +5 more | 2019-01-08 |
| 10168427 | Data readout via reflected ultrasound signals | Li-Wen Hung | 2019-01-01 |
| 10170584 | Nanosheet field effect transistors with partial inside spacers | Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Rajasekhar Venigalla | 2019-01-01 |
| 10170543 | Vertical fin field effect transistor with air gap spacers | Hari V. Mallela, Robert R. Robison, Rajasekhar Venigalla | 2019-01-01 |
| 10170485 | Three-dimensional stacked junctionless channels for dense SRAM | Michael A. Guillorn, Robert R. Robison, Rajasekhar Venigalla | 2019-01-01 |
| 10170477 | Forming MOSFET structures with work function modification | Ruqiang Bao, Gauri Karve, Derrick Liu, Robert R. Robison, Gen Tsutsui +1 more | 2019-01-01 |
| 10164119 | Vertical field effect transistors with protective fin liner during bottom spacer recess etch | Hari V. Mallela, Rajasekhar Venigalla | 2018-12-25 |
| 10147725 | Forming MOSFET structures with work function modification | Ruqiang Bao, Gauri Karve, Derrick Liu, Robert R. Robison, Gen Tsutsui +1 more | 2018-12-04 |
| 10128347 | Gate-all-around field effect transistor having multiple threshold voltages | Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Tenko Yamashita | 2018-11-13 |
| 10109535 | Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess ETCH | Hari V. Mallela, Rajasekhar Venigalla | 2018-10-23 |
| 10103226 | Method of fabricating tunnel transistors with abrupt junctions | Emre Alptekin, Hung H. Tran, Xiaobin Yuan | 2018-10-16 |
| 10096607 | Three-dimensional stacked junctionless channels for dense SRAM | Michael A. Guillorn, Robert R. Robison, Rajasekhar Venigalla | 2018-10-09 |
| 10083865 | Partial spacer for increasing self aligned contact process margins | Emre Alptekin, Ravikumar Ramachandran, Viraj Y. Sardesai | 2018-09-25 |
| 10068991 | Patterned sidewall smoothing using a pre-smoothed inverted tone pattern | Kafai Lai, Hari V. Mallela, Hiroyuki Miyazoe, Rajasekhar Venigalla | 2018-09-04 |
| 10032885 | Channel replacement and bimodal doping scheme for bulk finFet threshold voltage modulation with reduced performance penalty | Gauri Karve, Robert R. Robison | 2018-07-24 |
| 10001561 | Data readout via reflected ultrasound signals | Li-Wen Hung | 2018-06-19 |
| 9997411 | Formation of metal resistor and e-fuse | Cung D. Tran, Emre Alptekin, Viraj Y. Sardesai | 2018-06-12 |
| 9929047 | Partial spacer for increasing self aligned contact process margins | Emre Alptekin, Ravikumar Ramachandran, Viraj Y. Sardesai | 2018-03-27 |
| 9929058 | Vertical FETS with variable bottom spacer recess | Hari V. Mallela, Rajasekhar Venigalla | 2018-03-27 |
| 9911804 | Vertical fin field effect transistor with air gap spacers | Hari V. Mallela, Robert R. Robison, Rajasekhar Venigalla | 2018-03-06 |
| 9905694 | Fin-type field-effect transistors with strained channels | Henry K. Utomo, Yun-Yu Wang | 2018-02-27 |
| 9875939 | Methods of forming uniform and pitch independent fin recess | Yue Ke, Alexander Reznicek, Benjamin G. Moser, Dominic J. Schepis, Melissa A. Smith +2 more | 2018-01-23 |
| 9859421 | Vertical field effect transistor with subway etch replacement metal gate | Robert R. Robison, Rajasekhar Venigalla | 2018-01-02 |
| 9859384 | Vertical field effect transistors with metallic source/drain regions | Hari V. Mallela, Robert R. Robison, Rajasekhar Venigalla | 2018-01-02 |
| 9818877 | Embedded source/drain structure for tall finFET and method of formation | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo | 2017-11-14 |