Issued Patents All Time
Showing 26–50 of 165 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11481611 | RRAM crossbar array structure for multi-task learning | Takashi Ando, Hari V. Mallela | 2022-10-25 |
| 11456416 | Resistive switching memory cell | Praneet Adusumilli, Takashi Ando, Cheng Chi | 2022-09-27 |
| 11430954 | Resistance drift mitigation in non-volatile memory cell | Praneet Adusumilli, Anirban Chandra, Takashi Ando, Cheng Chi | 2022-08-30 |
| 11424362 | NCFETS with complimentary capacitance matching using stacked n-type and p-type nanosheets | Takashi Ando, Cheng Chi, Praneet Adusumilli | 2022-08-23 |
| 11342446 | Nanosheet field effect transistors with partial inside spacers | Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Rajasekhar Venigalla | 2022-05-24 |
| 11335730 | Vertical resistive memory device with embedded selectors | Takashi Ando, Praneet Adusumilli, Cheng Chi | 2022-05-17 |
| 11289573 | Contact resistance reduction in nanosheet device structure | Heng Wu, Dechao Guo, Ruqiang Bao, Junli Wang, Lan Yu +1 more | 2022-03-29 |
| 11245020 | Gate-all-around field effect transistor having multiple threshold voltages | Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Tenko Yamashita | 2022-02-08 |
| 11244864 | Reducing parasitic capacitance within semiconductor devices | Ruilong Xie, Alexander Reznicek, Kangguo Cheng | 2022-02-08 |
| 11211429 | Vertical intercalation device for neuromorphic computing | Jianshi Tang, Takashi Ando | 2021-12-28 |
| 11211452 | Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts | Ruilong Xie, Kangguo Cheng, Chanro Park, Juntao Li | 2021-12-28 |
| 11189786 | Tapered resistive memory with interface dipoles | Takashi Ando, Jianshi Tang, Praneet Adusumilli | 2021-11-30 |
| 11177436 | Resistive memory with embedded metal oxide fin for gradual switching | Takashi Ando, Praneet Adusumilli, Jianshi Tang | 2021-11-16 |
| 11164908 | Vertical intercalation device for neuromorphic computing | Jianshi Tang, Takashi Ando, Praneet Adusumilli | 2021-11-02 |
| 11145811 | Resistive memory with core and shell oxides and interface dipoles | Takashi Ando, Jianshi Tang, Praneet Adusumilli | 2021-10-12 |
| 11139299 | FinFET based ZRAM with convex channel region | Ravikumar Ramachandran | 2021-10-05 |
| 11137418 | Device test pad probe card structure with individual probe manipulation capability | Kushagra Sinha, Pablo Nieves | 2021-10-05 |
| 11125780 | Test probe assembly with fiber optic leads and photodetectors | Kushagra Sinha, Pablo Nieves | 2021-09-21 |
| 11119148 | Test probe assembly with fiber optic leads and photodetectors for testing semiconductor wafers | Pablo Nieves, Kushagra Sinha | 2021-09-14 |
| 11056391 | Subtractive vFET process flow with replacement metal gate and metallic source/drain | Hari V. Mallela, Robert R. Robison, Rajasekhar Venigalla | 2021-07-06 |
| 11050023 | CBRAM with controlled bridge location | Jianshi Tang, Takashi Ando, Praneet Adusumilli | 2021-06-29 |
| 11024709 | Vertical fin field effect transistor with air gap spacers | Hari V. Mallela, Robert R. Robison, Rajasekhar Venigalla | 2021-06-01 |
| 10957603 | Vertical FET devices with multiple channel lengths | Hari V. Mallela, Rajasekhar Venigalla | 2021-03-23 |
| 10915811 | Intercalation cells for multi-task learning | Takashi Ando, Jianshi Tang, Praneet Adusumilli | 2021-02-09 |
| 10903318 | External resistance reduction with embedded bottom source/drain for vertical transport FET | Choonghyun Lee, Jingyun Zhang, Miaomiao Wang | 2021-01-26 |