Issued Patents All Time
Showing 76–100 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8227870 | Method and structure for gate height scaling with high-k/metal gate technology | Ricardo A. Donaton, William K. Henson, Yue Liang | 2012-07-24 |
| 8227874 | Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes | James W. Adkisson, Jeffrey P. Gambino, Hongwen Yan | 2012-07-24 |
| 8183642 | Gate effective-workfunction modification for CMOS | Dae-Gyu Park, Rashmi Jha, Siddarth A. Krishnan, Naim Moumen, Vijay Narayanan +1 more | 2012-05-22 |
| 8138041 | In-situ silicon cap for metal gate electrode | Troy L. Graves-Abe, Rashmi Jha, Renee T. Mo, Keith Kwong Hon Wong | 2012-03-20 |
| 8138037 | Method and structure for gate height scaling with high-k/metal gate technology | Ricardo A. Donaton, William K. Henson, Yue Liang | 2012-03-20 |
| 8120144 | Method for forming dual high-K metal gate using photoresist mask and structures thereof | Rashmi Jha, Naim Moumen, Keith Kwong Hon Wong, Ying H. Tsang | 2012-02-21 |
| 8105892 | Thermal dual gate oxide device integration | Byeong Y. Kim | 2012-01-31 |
| 8106455 | Threshold voltage adjustment through gate dielectric stack modification | Brian J. Greene, Shu-Jen Han, William K. Henson, Yue Liang, Edward P. Maciejewski +3 more | 2012-01-31 |
| 8053306 | PFET with tailored dielectric and related methods and integrated circuit | Rick Carter, Rashmi Jha, Naim Moumen | 2011-11-08 |
| 8030716 | Self-aligned CMOS structure with dual workfunction | Dae-Gyu Park, Vijay Narayanan, Vamsi K. Paruchuri | 2011-10-04 |
| 8021939 | High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods | William K. Henson, Renee T. Mo, Jeffrey W. Sleight | 2011-09-20 |
| 8012863 | Transistors with gate stacks having metal electrodes | Paul Kirsch | 2011-09-06 |
| 7947549 | Gate effective-workfunction modification for CMOS | Dae-Gyu Park, Rashmi Jha, Siddarth A. Krishnan, Naim Moumen, Vijay Narayanan +1 more | 2011-05-24 |
| 7943457 | Dual metal and dual dielectric integration for metal high-k FETs | Wiliam K. Henson, Rashmi Jha, Yue Liang, Ravikumar Ramachandran, Richard S. Wise | 2011-05-17 |
| 7943460 | High-K metal gate CMOS | Renee T. Mo, Huiming Bu, William K. Henson, Mukesh V. Khare, Vijay Narayanan | 2011-05-17 |
| 7915115 | Method for forming dual high-k metal gate using photoresist mask and structures thereof | Rashmi Jha, Naim Moumen, Keith Kwong Hon Wong, Ying H. Tsang | 2011-03-29 |
| 7871933 | Combined stepper and deposition tool | Joseph F. Shepard, Jr. | 2011-01-18 |
| 7872317 | Dual metal gate self-aligned integration | Alessandro C. Callegari, Bruce B. Doris, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen | 2011-01-18 |
| 7863126 | Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region | Dae-Gyu Park, Vijay Narayanan, Vamsi K. Paruchuri | 2011-01-04 |
| 7863124 | Residue free patterned layer formation method applicable to CMOS structures | Bruce B. Doris, William K. Henson, Hongwen Yan, Ying Zhang | 2011-01-04 |
| 7863123 | Direct contact between high-κ/metal gate and wiring process flow | Huiming Bu, Ricardo A. Donaton, Naim Moumen, Hongwen Yan | 2011-01-04 |
| 7838908 | Semiconductor device having dual metal gates and method of manufacture | Unoh Kwon, Siddarth A. Krishnan, Takashi Ando, Martin M. Frank, William K. Henson +5 more | 2010-11-23 |
| 7833849 | Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode | Alessandro C. Callegari, Tze-Chiang Chen, Bruce B. Doris, Young-Hee Kim, Vijay Narayanan +3 more | 2010-11-16 |
| 7790559 | Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes | James W. Adkisson, Jeffrey P. Gambino, Hongwen Yan | 2010-09-07 |
| 7781321 | Electroless metal deposition for dual work function | Jeffrey P. Gambino, Renee T. Mo | 2010-08-24 |