Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7485965 | Through via in ultra high resistivity wafer and related methods | Louis D. Lanzerotti, Yun Shi, Steven H. Voldman | 2009-02-03 |
| 7239376 | Method and apparatus for correcting gravitational sag in photomasks used in the production of electronic devices | Michael S. Hibbs, Kenneth Racette | 2007-07-03 |
| 6812122 | Method for forming a voltage programming element | Claude L. Bertin, Erik L. Hedberg, Russell J. Houghton, Rick L. Mohler, William R. Tonti +1 more | 2004-11-02 |
| 6633055 | Electronic fuse structure and method of manufacturing | Claude L. Bertin, Erik L. Hedberg, Timothy D. Sullivan, William R. Tonti | 2003-10-14 |
| 6518145 | Methods to control the threshold voltage of a deep trench corner device | Johann Alsmeier, George R. Goth, Victor R. Nastasi, James A. O'Neill, Paul C. Parries | 2003-02-11 |
| 6483172 | Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states | Donna R. Cote, William J. Cote, Son V. Nguyen, Markus Kirchhoff, Manfred Hauf | 2002-11-19 |
| 6388305 | Electrically programmable antifuses and methods for forming the same | Claude L. Bertin, Erik L. Hedberg, Russell J. Houghton, Rick L. Mohler, William R. Tonti +1 more | 2002-05-14 |
| 6372573 | Self-aligned trench capacitor capping process for high density DRAM cells | Masami Aoki, Hirofumi Inoue, Bruce W. Porth, Victor R. Nastasi, Emily E. Fisch +1 more | 2002-04-16 |
| 6361402 | Method for planarizing photoresist | Donald F. Canaperi, Rangarajan Jagannathan, Mahadevaiyer Krishnan, Uma Satyendra, Matthew Sendelbach +2 more | 2002-03-26 |
| 6121106 | Method for forming an integrated trench capacitor | Wayne F. Ellis, Russell J. Houghton, William R. Tonti | 2000-09-19 |
| 6103592 | Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas | Bernhard Fiegl, Walter Glashauser, Frank Prein | 2000-08-15 |
| 5976982 | Methods for protecting device components from chemical mechanical polish induced defects | Wolfgang Bergner, Bernhard Fiegl, George R. Goth, Paul C. Parries, Matthew Sendelbach +3 more | 1999-11-02 |
| 5824580 | Method of manufacturing an insulated gate field effect transistor | Manfred Hauf, Victor R. Nastasi | 1998-10-20 |
| 5804490 | Method of filling shallow trenches | Bernhard Fiegl, Walter Glashauser, Victor R. Nastasi | 1998-09-08 |
| 5757059 | Insulated gate field effect transistor | Manfred Hauf, Victor R. Nastasi | 1998-05-26 |
| 5721448 | Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material | Manfred Hauf, Victor R. Nastasi | 1998-02-24 |