Issued Patents All Time
Showing 76–100 of 143 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7700410 | Chip-in-slot interconnect for 3D chip stacks | Timothy J. Dalton, Edmund J. Sprogis, Anthony K. Stamper, Richard Q. Williams | 2010-04-20 |
| 7692944 | 3-dimensional integrated circuit architecture, structure and method for fabrication thereof | Paul W. Coteus, Philip G. Emma | 2010-04-06 |
| 7684224 | Structure comprising 3-dimensional integrated circuit architecture, circuit structure, and instructions for fabrication thereof | Paul W. Coteus, Philip G. Emma | 2010-03-23 |
| 7670927 | Double-sided integrated circuit chips | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Stephen E. Luce +1 more | 2010-03-02 |
| 7652947 | Back-gate decode personalization | Wilfried E. Haensch | 2010-01-26 |
| 7642813 | Error correcting logic system | Philip G. Emma, John A. Fifield, Paul D. Kartschoke, William A. Klaasen, Norman J. Rohrer | 2010-01-05 |
| 7633819 | Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator | Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Keith R. Williams | 2009-12-15 |
| 7629233 | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement | Jeffery Sleight, Min Yang | 2009-12-08 |
| 7605429 | Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement | Jeffrey W. Sleight, Min Yang | 2009-10-20 |
| 7521950 | Wafer level I/O test and repair enabled by I/O layer | Paul W. Coteus, Ibrahim M. Elfadel, Philip G. Emma, Daniel J. Friedman, Ruchir Puri +3 more | 2009-04-21 |
| 7508250 | Testing for normal or reverse temperature related delay variations in integrated circuits | David Wolpert | 2009-03-24 |
| 7471115 | Error correcting logic system | Philip G. Emma, John A. Fifield, Paul D. Kartschoke, William A. Klaasen, Norman J. Rohrer | 2008-12-30 |
| 7462509 | Dual-sided chip attached modules | Timothy J. Dalton, Timothy H. Daubenspeck, Jeffrey P. Gambino, Mark D. Jaffe, Christopher D. Muzzy +3 more | 2008-12-09 |
| 7460422 | Determining history state of data based on state of partially depleted silicon-on-insulator | Kenneth J. Goodnow, Clarence R. Ogilvis, Sebastian T. Ventrone, Keith R. Williams | 2008-12-02 |
| 7454642 | Method and architecture for power management of an electronic device | Kenneth J. Goodnow, Clarence R. Ogilvie, Keith R. Williams, Sebastian T. Ventrone | 2008-11-18 |
| 7408798 | 3-dimensional integrated circuit architecture, structure and method for fabrication thereof | Paul W. Coteus, Philip G. Emma | 2008-08-05 |
| 7402854 | Three-dimensional cascaded power distribution in a semiconductor device | Paul W. Coteus, Philip G. Emma, Allan M. Hartstein, Stephen V. Kosonocky, Ruchir Puri +1 more | 2008-07-22 |
| 7397718 | Determining relative amount of usage of data retaining device based on potential of charge storing device | Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Keith R. Williams | 2008-07-08 |
| 7389478 | System and method for designing a low leakage monotonic CMOS logic circuit | Norman J. Rohrer | 2008-06-17 |
| 7381627 | Dual wired integrated circuit chips | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Anthony K. Stamper | 2008-06-03 |
| 7368355 | FinFET transistor and circuit | Edward J. Nowak, BethAnn Rainey | 2008-05-06 |
| 7336102 | Error correcting logic system | Philip G. Emma, John A. Fifield, Paul D. Kartschoke, William A. Klaasen, Norman J. Rohrer | 2008-02-26 |
| 7323382 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same | John A. Bracchitta, William J. Cote, Tak H. Ning, Wilbur D. Pricer | 2008-01-29 |
| 7298161 | Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability | Ronald J. Bolam, Edward J. Nowak, Alvin W. Strong, Jody Van Horn, Ernest Y. Wu | 2007-11-20 |
| 7285477 | Dual wired integrated circuit chips | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Anthony K. Stamper | 2007-10-23 |