Issued Patents All Time
Showing 26–50 of 143 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8487427 | Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly | Thomas J. Brunschwiler, Bruno Michel | 2013-07-16 |
| 8471306 | Double-sided integrated circuit chips | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Stephen E. Luce +1 more | 2013-06-25 |
| 8441042 | BEOL compatible FET structure | Christy S. Tyberg, Katherine L. Saenger, Jack O. Chu, Harold J. Hovel, Robert L. Wisnieff +1 more | 2013-05-14 |
| 8421126 | Double-sided integrated circuit chips | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Stephen E. Luce +1 more | 2013-04-16 |
| 8417503 | System and method for target-based compact modeling | Josef S. Watts, Richard Q. Williams | 2013-04-09 |
| 8347260 | Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage | James A. Culp, Leah M. P. Pastel, Kirk D. Peterson, Norman J. Rohrer | 2013-01-01 |
| 8343814 | Compact multi-port cam cell implemented in 3D vertical integration | Robert J. Bucki, Jagreet S. Atwal, Joseph S. Barnes, Eric F. Robinson | 2013-01-01 |
| 8298876 | Methods for normalizing strain in semiconductor devices and strain normalized semiconductor devices | Bruce Balch, John J. Ellis-Monaghan, Nazmul Habib | 2012-10-30 |
| 8298906 | Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch | Francis R. White | 2012-10-30 |
| 8294149 | Test structure and methodology for three-dimensional semiconductor structures | Jerome L. Cann, Christopher McCall Durham, Paul D. Kartschoke, Peter Juergen Klim, Donald L. Wheater | 2012-10-23 |
| 8263472 | Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices | John E. Barth, Jr. | 2012-09-11 |
| 8250303 | Adaptive linesize in a cache | Moinuddin K. Qureshi | 2012-08-21 |
| 8234554 | Soft error correction in sleeping processors | Norman J. Rohrer | 2012-07-31 |
| 8232190 | Three dimensional vertical E-fuse structures and methods of manufacturing the same | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Stephen E. Luce, Anthony K. Stamper | 2012-07-31 |
| 8133772 | Deep trench capacitor for SOI CMOS devices for soft error immunity | John E. Barth, Jr., Ethan H. Cannon, Francis R. White | 2012-03-13 |
| 8106505 | Assembly including plural through wafer vias, method of cooling the assembly and method of fabricating the assembly | Thomas J. Brunschwiler, Bruno Michel | 2012-01-31 |
| 8097525 | Vertical through-silicon via for a semiconductor structure | John E. Barth, Jr. | 2012-01-17 |
| 8080851 | Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices | John E. Barth, Jr. | 2011-12-20 |
| 8053303 | SOI body contact using E-DRAM technology | John E. Barth, Jr., Francis R. White | 2011-11-08 |
| 8053819 | Three-dimensional cascaded power distribution in a semiconductor device | Paul W. Coteus, Philip G. Emma, Allan M. Hartstein, Stephen V. Kosonocky, Ruchir Puri +1 more | 2011-11-08 |
| 8055822 | Multicore processor having storage for core-specific operational data | Nazmul Habib, Norman J. Rohrer | 2011-11-08 |
| 8019970 | Three-dimensional networking design structure | Timothy J. Dalton, Marc R. Faucher, Peter A. Sandon | 2011-09-13 |
| 8013342 | Double-sided integrated circuit chips | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Stephen E. Luce +1 more | 2011-09-06 |
| 7996810 | System and method for designing a low leakage monotonic CMOS logic circuit | Norman J. Rohrer | 2011-08-09 |
| 7989312 | Double-sided integrated circuit chips | Timothy J. Dalton, Jeffrey P. Gambino, Mark D. Jaffe, Paul D. Kartschoke, Stephen E. Luce +1 more | 2011-08-02 |