Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8298906 | Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch | Kerry Bernstein | 2012-10-30 |
| 8133772 | Deep trench capacitor for SOI CMOS devices for soft error immunity | John E. Barth, Jr., Kerry Bernstein, Ethan H. Cannon | 2012-03-13 |
| 8053303 | SOI body contact using E-DRAM technology | John E. Barth, Jr., Kerry Bernstein | 2011-11-08 |
| 7989893 | SOI body contact using E-DRAM technology | John E. Barth, Jr., Kerry Bernstein | 2011-08-02 |
| 7989865 | Deep trench capacitor for SOI CMOS devices for soft error immunity | John E. Barth, Jr., Kerry Bernstein, Ethan H. Cannon | 2011-08-02 |
| 7812388 | Deep trench capacitor and method of making same | Timothy W. Kemerer, Robert M. Rassel, Steven M. Shank | 2010-10-12 |
| 7694262 | Deep trench capacitor and method of making same | Timothy W. Kemerer, Robert M. Rassel, Steven M. Shank | 2010-04-06 |
| 6680259 | Dual layer etch stop barrier | Chung H. Lam, Eric Lee | 2004-01-20 |
| 6548418 | Dual layer etch stop barrier | Chung H. Lam, Eric Lee | 2003-04-15 |
| 6420777 | Dual layer etch stop barrier | Chung H. Lam, Eric Lee | 2002-07-16 |
| 6335272 | Buried butted contact and method for fabricating | Archibald J. Allen, Jerome B. Lasky, Randy W. Mann, Jed H. Rankin | 2002-01-01 |
| 6174763 | Three-dimensional SRAM trench structure and fabrication method therefor | Kenneth E. Beilstein, Jr., Claude L. Bertin, John Cronin | 2001-01-16 |
| 6153934 | Buried butted contact and method for fabricating | Archibald J. Allen, Jerome B. Lasky, Randy W. Mann, Jed H. Rankin | 2000-11-28 |
| 6140171 | FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication | Archibald J. Allen, Jerome B. Lasky, Randy W. Mann, John J. Pekarik, Jed H. Rankin +1 more | 2000-10-31 |
| 6038168 | Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor | Archibald J. Allen, Jerome B. Lasky, John J. Pekarik, Jed H. Rankin | 2000-03-14 |
| 6022766 | Semiconductor structure incorporating thin film transistors, and methods for its manufacture | Bomy Chen, Subhash B. Kulkarni, Jerome B. Lasky, Randy W. Mann, Edward J. Nowak +1 more | 2000-02-08 |
| 5675185 | Semiconductor structure incorporating thin film transistors with undoped cap oxide layers | Bomy Chen, Subhash B. Kulkarni, Jerome B. Lasky, Randy W. Mann, Edward J. Nowak +1 more | 1997-10-07 |
| 5670803 | Three-dimensional SRAM trench structure and fabrication method therefor | Kenneth E. Beilstein, Jr., Claude L. Bertin, John Cronin | 1997-09-23 |
| 5270261 | Three dimensional multichip package methods of fabrication | Claude L. Bertin, Paul A. Farrar, Howard L. Kalter, Gordon A. Kelley, Jr., Willem B. van der Hoeven | 1993-12-14 |
| 5202754 | Three-dimensional multichip packages and methods of fabrication | Claude L. Bertin, Paul A. Farrar, Howard L. Kalter, Gordon A. Kelley, Jr., Willem B. van der Hoeven | 1993-04-13 |
| 5096849 | Process for positioning a mask within a concave semiconductor structure | Kenneth E. Beilstein, Jr., Claude L. Bertin | 1992-03-17 |
| 5055898 | DRAM memory cell having a horizontal SOI transfer device disposed over a buried storage node and fabrication methods therefor | Kenneth E. Beilstein, Jr., Claude L. Bertin, John R. Pessetto | 1991-10-08 |
| 4799990 | Method of self-aligning a trench isolation structure to an implanted well region | Michael L. Kerbaugh, Charles W. Koburger, III, Jerome B. Lasky, Paul C. Parries | 1989-01-24 |
| 4558508 | Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step | Wayne Kinney, Charles W. Koburger, III, Jerome B. Lasky, Larry A. Nesbit, Ronald R. Troutman | 1985-12-17 |
| 4527325 | Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing | Henry J. Geipel, Jr., Charles A. Schaefer, John M. Wursthorn | 1985-07-09 |