Issued Patents All Time
Showing 1,326–1,350 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10056289 | Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap | Zuoguang Liu, Sebastian Naczas, Heng Wu, Peng Xu | 2018-08-21 |
| 10056255 | Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy | Juntao Li | 2018-08-21 |
| 10056254 | Methods for removal of selected nanowires in stacked gate all around architecture | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-08-21 |
| 10050141 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-08-14 |
| 10050121 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-08-14 |
| 10050107 | Nanosheet transistors on bulk material | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-08-14 |
| 10049945 | Forming a CMOS with dual strained channels | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-08-14 |
| 10043900 | Vertical transport Fin field effect transistors on a substrate with varying effective gate lengths | Zhenxing Bi, Juntao Li, Peng Xu | 2018-08-07 |
| 10043878 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-08-07 |
| 10043874 | Uniform vertical field effect transistor spacers | Juntao Li | 2018-08-07 |
| 10043801 | Air gap spacer for metal gates | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2018-08-07 |
| 10043746 | Fabrication of vertical fuses from vertical fins | James J. Demarest, Juntao Li | 2018-08-07 |
| 10038075 | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region | Stephane Allegret-Maret, Bruce B. Doris, Prasanna Khare, Qing Liu, Nicolas Loubet | 2018-07-31 |
| 10038066 | Uniform vertical field effect transistor spacers | Juntao Li | 2018-07-31 |
| 10038053 | Methods for removal of selected nanowires in stacked gate all around architecture | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-07-31 |
| 10037919 | Integrated single-gated vertical field effect transistor (VFET) and independent double-gated VFET | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2018-07-31 |
| 10037916 | Semiconductor fins for finFET devices and sidewall image transfer (SIT) processes for manufacturing the same | Veeraraghavan S. Basker, Theodorus E. Standaert | 2018-07-31 |
| 10032912 | Semiconductor integrated structure having an epitaxial SiGe layer extending from silicon-containing regions formed between segments of oxide regions | Pierre Morin, Jody A. Fronheiser, Xiuyu Cai, Juntao Li, Shogo Mochizuki +3 more | 2018-07-24 |
| 10032909 | Vertical transistor having uniform bottom spacers | Juntao Li, Geng Wang, Qintao Zhang | 2018-07-24 |
| 10032897 | Single electron transistor with self-aligned Coulomb blockade | Qing Cao, Zhengwen Li, Fei Liu | 2018-07-24 |
| 10032884 | Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita | 2018-07-24 |
| 10032858 | Nanosheet capacitor | Zhenxing Bi, Dongbing Shao, Zheng Xu | 2018-07-24 |
| 10032856 | Nanosheet capacitor | Ruqiang Bao, Zhenxing Bi, Zheng Xu | 2018-07-24 |
| 10032773 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Ali Khakifirooz, Charles W. Koburger, III | 2018-07-24 |
| 10032769 | Cmos compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-07-24 |