KC

Kangguo Cheng

IBM: 2575 patents #1 of 70,183Top 1%
Globalfoundries: 269 patents #3 of 4,424Top 1%
TE Tessera: 34 patents #14 of 271Top 6%
SS Stmicroelectronics Sa: 19 patents #57 of 1,676Top 4%
AS Adeia Semiconductor Solutions: 13 patents #1 of 57Top 2%
ET Elpis Technologies: 12 patents #1 of 121Top 1%
CEA: 6 patents #716 of 7,956Top 9%
GU Globalfoundries U.S.: 5 patents #206 of 665Top 35%
Samsung: 5 patents #22,466 of 75,807Top 30%
RE Renesas Electronics: 4 patents #1,016 of 4,529Top 25%
IB International Business: 1 patents #4 of 119Top 4%
📍 Schenectady, NY: #1 of 1,353 inventorsTop 1%
🗺 New York: #1 of 115,490 inventorsTop 1%
Overall (All Time): #5 of 4,157,543Top 1%
2819
Patents All Time

Issued Patents All Time

Showing 1,376–1,400 of 2,819 patents

Patent #TitleCo-InventorsDate
10002926 Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy Pouya Hashemi, Alexander Reznicek 2018-06-19
10002925 Strained semiconductor device Peng Xu 2018-06-19
10002924 Devices including high percentage SiGe fins formed at a tight pitch and methods of manufacturing same Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek 2018-06-19
10002923 Techniques for forming finFET transistors with same fin pitch and different source/drain epitaxy configurations Peng Xu 2018-06-19
10002868 Vertical fin resistor devices Zhenxing Bi, Peng Xu 2018-06-19
10002809 Top contact resistance measurement in vertical FETs Zuoguang Liu, Xin Miao, Wenyu Xu, Chen Zhang 2018-06-19
10002803 Flipped vertical field-effect-transistor Xin Miao, Wenyu Xu, Chen Zhang 2018-06-19
10002795 Method and structure for forming vertical transistors with shared gates and separate gates Zhenxing Bi, Juntao Li, Peng Xu 2018-06-19
10002794 Multiple gate length vertical field-effect-transistors Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek 2018-06-19
9997618 Integrated strained stacked nanosheet FET Ramachandra Divakaruni, Juntao Li, Xin Miao 2018-06-12
9997606 Fully depleted SOI device for reducing parasitic back gate capacitance Ramachandra Divakaruni 2018-06-12
9997597 Vertical single electron transistor formed by condensation Xin Miao, Wenyu Xu, Chen Zhang 2018-06-12
9997540 Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim 2018-06-12
9997421 Top contact resistance measurement in vertical FETS Zuoguang Liu, Xin Miao, Wenyu Xu, Chen Zhang 2018-06-12
9991365 Forming vertical transport field effect transistors with uniform bottom spacer thickness Xuefeng Liu, Peng Xu, Yongan Xu 2018-06-05
9991334 Nanosheet capacitor Zhenxing Bi, Dongbing Shao, Zheng Xu 2018-06-05
9991328 Tunable on-chip nanosheet resistor Zhenxing Bi, Wei Wang, Zheng Xu 2018-06-05
9991254 Forming horizontal bipolar junction transistor compatible with nanosheets Juntao Li, Geng Wang, Qintao Zhang 2018-06-05
9991168 Germanium dual-fin field effect transistor Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek 2018-06-05
9991166 Wimpy device by selective laser annealing Nicolas Loubet, Xin Miao, Alexander Reznicek 2018-06-05
9991117 Fin patterns with varying spacing without fin cut Marc A. Bergendahl, John R. Sporre, Sean Teehan 2018-06-05
9985138 Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors Marc A. Bergendahl, Eric R. Miller, John R. Sporre, Sean Teehan 2018-05-29
9985135 Replacement low-k spacer Xiuyu Cai, Ali Khakifirooz, Ruilong Xie 2018-05-29
9985117 Method and structure for forming dielectric isolated finFET with improved source/drain epitaxy Juntao Li 2018-05-29
9985107 Method and structure for forming MOSFET with reduced parasitic capacitance Peng Xu, Chen Zhang 2018-05-29