KC

Kangguo Cheng

IBM: 2575 patents #1 of 70,183Top 1%
Globalfoundries: 269 patents #3 of 4,424Top 1%
TE Tessera: 34 patents #14 of 271Top 6%
SS Stmicroelectronics Sa: 19 patents #57 of 1,676Top 4%
AS Adeia Semiconductor Solutions: 13 patents #1 of 57Top 2%
ET Elpis Technologies: 12 patents #1 of 121Top 1%
CEA: 6 patents #716 of 7,956Top 9%
GU Globalfoundries U.S.: 5 patents #206 of 665Top 35%
Samsung: 5 patents #22,466 of 75,807Top 30%
RE Renesas Electronics: 4 patents #1,016 of 4,529Top 25%
IB International Business: 1 patents #4 of 119Top 4%
📍 Schenectady, NY: #1 of 1,353 inventorsTop 1%
🗺 New York: #1 of 115,490 inventorsTop 1%
Overall (All Time): #5 of 4,157,543Top 1%
2819
Patents All Time

Issued Patents All Time

Showing 1,151–1,175 of 2,819 patents

Patent #TitleCo-InventorsDate
10224329 Forming gates with varying length using sidewall image transfer Juntao Li, Geng Wang, Qintao Zhang 2019-03-05
10224277 Dielectric thermal conductor for passivating eFuse and metal resistor Qing Cao, Zhengwen Li, Fei Liu 2019-03-05
10224247 FinFET devices Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang 2019-03-05
10224246 Multi-layer filled gate cut to prevent power rail shorting to gate structure Hao Tang, Peng Xu 2019-03-05
10224207 Forming a contact for a tall fin transistor Ruilong Xie, Tenko Yamashita 2019-03-05
10217869 Semiconductor structure including low-K spacer material Xiuyu Cai, Ali Khakifirooz, Ruilong Xie 2019-02-26
10217868 Airgap spacers Zuoguang Liu, Chun Wing Yeung 2019-02-26
10217867 Uniform fin dimensions using fin cut hardmask Peng Xu 2019-02-26
10217845 Vertical field effect transistors with bottom source/drain epitaxy Xin Miao, Wenyu Xu, Chen Zhang 2019-02-26
10217843 Fabrication of vertical field effect transistor structure with strained channels Juntao Li 2019-02-26
10217841 Forming an uniform L-shaped inner spacer for a vertical transport fin field effect transistor (VT FinFET) Juntao Li, Peng Xu, Jingyun Zhang 2019-02-26
10217840 Replacement metal gate structures Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang 2019-02-26
10217818 Method of formation of germanium nanowires on bulk substrates Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek 2019-02-26
10217707 Trench contact resistance reduction Zhenxing Bi, Juntao Li, Peng Xu 2019-02-26
10217672 Vertical transistor devices with different effective gate lengths Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita 2019-02-26
10217658 Method and structure for minimizing fin reveal variation in FinFET transistor Zhenxing Bi, Juntao Li, Hao Tang 2019-02-26
10217634 Fin patterns with varying spacing without fin cut Marc A. Bergendahl, John R. Sporre, Sean Teehan 2019-02-26
10211320 Fin cut without residual fin defects Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis 2019-02-19
10211302 Field effect transistor devices having gate contacts formed in active region overlapping source/drain contacts Peng Xu 2019-02-19
10211288 Vertical transistors with multiple gate lengths Zhenxing Bi, Peng Xu, Zheng Xu 2019-02-19
10211092 Transistor with robust air spacer Chanro Park 2019-02-19
10211055 Fin patterns with varying spacing without fin cut Marc A. Bergendahl, John R. Sporre, Sean Teehan 2019-02-19
10209367 Colorimetric radiation dosimetry Qing Cao, Zhengwen Li, Fei Liu 2019-02-19
10204916 Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET) Veeraraghavan S. Basker, Ali Khakifirooz 2019-02-12
10204836 Porous silicon relaxation medium for dislocation free CMOS devices Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana 2019-02-12