Issued Patents All Time
Showing 1,176–1,200 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10204835 | Fabrication of a vertical fin field effect transistor with reduced dimensional variations | — | 2019-02-12 |
| 10199503 | Under-channel gate transistors | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-02-05 |
| 10199480 | Controlling self-aligned gate length in vertical transistor replacement gate flow | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-02-05 |
| 10199464 | Techniques for VFET top source/drain epitaxy | Cheng Chi, Chi-Chun Liu, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2019-02-05 |
| 10199278 | Vertical field effect transistor (FET) with controllable gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2019-02-05 |
| 10199220 | Semiconductor structure having insulator pillars and semiconductor material on substrate | Alexander Reznicek, Dominic J. Schepis, Bruce B. Doris, Pouya Hashemi | 2019-02-05 |
| 10177256 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-01-08 |
| 10177237 | Etch stop for airgap protection | Ruilong Xie, Tenko Yamashita | 2019-01-08 |
| 10177235 | Nano-sheet transistors with different threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-01-08 |
| 10177223 | FinFET with reduced parasitic capacitance | Darsen D. Lu, Xin Miao, Tenko Yamashita | 2019-01-08 |
| 10177168 | Fin field-effect transistor having an oxide layer under one or more of the plurality of fins | Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis | 2019-01-08 |
| 10177154 | Structure and method to prevent EPI short between trenches in FinFET eDRAM | Michael V. Aquilino, Veeraraghavan S. Basker, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim +5 more | 2019-01-08 |
| 10177046 | Vertical FET with different channel orientations for NFET and PFET | Xin Miao, Wenyu Xu, Chen Zhang | 2019-01-08 |
| 10170640 | FinFET transistor gate and epitaxy formation | Ruqiang Bao, Zhenxing Bi, Zheng Xu | 2019-01-01 |
| 10170637 | Perfectly symmetric gate-all-around FET on suspended nanowire | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2019-01-01 |
| 10170628 | Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance and contact resistance due to wrap-around structure of source/drain regions | Ramachandra Divakaruni | 2019-01-01 |
| 10170619 | Vertical schottky contact FET | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-01-01 |
| 10170618 | Vertical transistor with reduced gate-induced-drain-leakage current | Xin Miao, Peng Xu, Chen Zhang | 2019-01-01 |
| 10170596 | Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch | Peng Xu | 2019-01-01 |
| 10170595 | Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch | Peng Xu | 2019-01-01 |
| 10170590 | Vertical field effect transistors with uniform threshold voltage | Xin Miao, Heng Wu, Peng Xu | 2019-01-01 |
| 10170587 | Heterogeneous source drain region and extension region | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2019-01-01 |
| 10170586 | Unipolar spacer formation for finFETs | Peng Xu, Jie Yang | 2019-01-01 |
| 10170583 | Forming a gate contact in the active area | Ruilong Xie, Tenko Yamashita | 2019-01-01 |
| 10170575 | Vertical transistors with buried metal silicide bottom contact | Tak H. Ning, Alexander Reznicek | 2019-01-01 |