Issued Patents All Time
Showing 1,226–1,250 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157935 | Nanosheet capacitor | Juntao Li, Geng Wang, Qintao Zhang | 2018-12-18 |
| 10158021 | Vertical pillar-type field effect transistor and method | Ruilong Xie, Tenko Yamashita | 2018-12-18 |
| 10157797 | FinFET devices | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-12-18 |
| 10157912 | CMOS compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-12-18 |
| 10157745 | High aspect ratio gates | Sivananda K. Kanakasabapathy, Peng Xu | 2018-12-18 |
| 10153157 | P-FET with graded silicon-germanium channel | Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek | 2018-12-11 |
| 10153367 | Gate length controlled vertical FETs | Xin Miao, Wenyu Xu, Chen Zhang | 2018-12-11 |
| 10147804 | High density vertical nanowire stack for field effect transistor | Ali Khakifirooz, Juntao Li | 2018-12-04 |
| 10147808 | Techniques for forming vertical tunneling FETS | Juntao Li, Xin Miao, Peng Xu | 2018-12-04 |
| 10147741 | FinFET with stacked faceted S/D epitaxy for improved contact resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-12-04 |
| 10147635 | Different shallow trench isolation fill in fin and non-fin regions of finFET | Peng Xu, Chen Zhang | 2018-12-04 |
| 10147651 | Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels | Zhenxing Bi, Peng Xu, Jie Yang | 2018-12-04 |
| 10147679 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2018-12-04 |
| 10147602 | Double aspect ratio trapping | Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2018-12-04 |
| 10141441 | Vertical transistor with back bias and reduced parasitic capacitance | Xin Miao, Peng Xu, Chen Zhang | 2018-11-27 |
| 10141445 | Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors | Marc A. Bergendahl, Eric R. Miller, John R. Sporre, Sean Teehan | 2018-11-27 |
| 10141428 | Fin formation in fin field effect transistors | Bruce B. Doris, Hong He, Ali Khakifirooz, Yunpeng Yin | 2018-11-27 |
| 10141448 | Vertical FETs with different gate lengths and spacer thicknesses | Xin Miao, Chen Zhang, Wenyu Xu | 2018-11-27 |
| 10141420 | Transistors with dielectric-isolated source and drain regions | Choonghyun Lee, Juntao Li, Peng Xu | 2018-11-27 |
| 10141313 | FinFET with uniform shallow trench isolation recess | Zhenxing Bi, Juntao Li, Peng Xu | 2018-11-27 |
| 10141320 | Multiple-bit electrical fuses | Ramachandra Divakaruni | 2018-11-27 |
| 10141309 | Tight pitch inverter using vertical transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-11-27 |
| 10141338 | Strained CMOS on strain relaxation buffer substrate | Balasubramanian Pranatharthiharan, Juntao Li | 2018-11-27 |
| 10141230 | Method and structure to enable dual channel Fin critical dimension control | Marc A. Bergendahl, John R. Sporre, Sean Teehan | 2018-11-27 |
| 10141234 | Flipped vertical field-effect-transistor | Xin Miao, Wenyu Xu, Chen Zhang | 2018-11-27 |