Issued Patents All Time
Showing 1,251–1,275 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141234 | Flipped vertical field-effect-transistor | Xin Miao, Wenyu Xu, Chen Zhang | 2018-11-27 |
| 10141309 | Tight pitch inverter using vertical transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-11-27 |
| 10141313 | FinFET with uniform shallow trench isolation recess | Zhenxing Bi, Juntao Li, Peng Xu | 2018-11-27 |
| 10134762 | Embedded security circuit formed by directed self-assembly | Chi-Chun Liu | 2018-11-20 |
| 10134859 | Transistor with asymmetric spacers | Zhenxing Bi, Heng Wu, Peng Xu | 2018-11-20 |
| 10134760 | FinFETs with various fin height | Terence B. Hook, Xin Miao, Balasubramanian Pranatharthiharan | 2018-11-20 |
| 10134866 | Field effect transistor air-gap spacers with an etch-stop layer | Xin Miao, Wenyu Xu, Chen Zhang | 2018-11-20 |
| 10134595 | High aspect ratio gates | Sivananda K. Kanakasabapathy, Peng Xu | 2018-11-20 |
| 10134874 | Vertical field effect transistors with bottom source/drain epitaxy | Xin Miao, Wenyu Xu, Chen Zhang | 2018-11-20 |
| 10128235 | Asymmetrical vertical transistor | Zhenxing Bi, Juntao Li, Peng Xu | 2018-11-13 |
| 10128238 | Integrated circuit having oxidized gate cut region and method to fabricate same | Andrew M. Greene, Peng Xu | 2018-11-13 |
| 10128122 | Stacked nanowires | Zhenxing Bi, Juntao Li, Xin Miao | 2018-11-13 |
| 10121789 | Self-aligned source/drain contacts | Praneet Adusumilli, Emre Alptekin, Balasubramanian Pranatharthiharan, Shom Ponoth | 2018-11-06 |
| 10121879 | Forming odd number of fins by sidewall imaging transfer | Xin Miao | 2018-11-06 |
| 10115805 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Juntao Li, Zuoguang Liu, Xin Miao | 2018-10-30 |
| 10115629 | Air gap spacer formation for nano-scale semiconductor devices | Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen +2 more | 2018-10-30 |
| 10109709 | P-FET with strained silicon-germanium channel | Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi | 2018-10-23 |
| 10109722 | Etch-resistant spacer formation on gate structure | Ruilong Xie, Zhenxing Bi, Pietro Montanini, Eric R. Miller, Balasubramanian Pranatharthiharan +2 more | 2018-10-23 |
| 10109491 | Vertical FET with selective atomic layer deposition gate | Xin Miao, Wenyu Xu, Chen Zhang | 2018-10-23 |
| 10103063 | Forming a hybrid channel nanosheet semiconductor structure | Peng Xu | 2018-10-16 |
| 10103243 | Unipolar spacer formation for finFETS | Peng Xu, Jie Yang | 2018-10-16 |
| 10103246 | Fabrication of a vertical fin field effect transistor (vertical finFET) with a self-aligned gate and fin edges | Xin Miao, Wenyu Xu, Chen Zhang | 2018-10-16 |
| 10103247 | Vertical transistor having buried contact, and contacts using work function metals and silicides | Ruilong Xie, Hui Zang, Tenko Yamashita, Chun-Chen Yeh | 2018-10-16 |
| 10096698 | Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy | Juntao Li | 2018-10-09 |
| 10096674 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Xin Miao, Ruilong Xie, Tenko Yamashita | 2018-10-09 |