Issued Patents All Time
Showing 1,126–1,150 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10242916 | Stress memorization technique for strain coupling enhancement in bulk FINFET device | Juntao Li, Chun-Chen Yeh | 2019-03-26 |
| 10242881 | Self-aligned single dummy fin cut with tight pitch | Cheng Chi, Chi-Chun Liu, Peng Xu | 2019-03-26 |
| 10236382 | Multiple finFET formation with epitaxy separation | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-19 |
| 10236381 | IFinFET | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-19 |
| 10236380 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236364 | Tunnel transistor | Peng Xu, Heng Wu, Zhenxing Bi | 2019-03-19 |
| 10236363 | Vertical field-effect transistors with controlled dimensions | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2019-03-19 |
| 10236359 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236355 | Fabrication of a vertical fin field effect transistor with a reduced contact resistance | Xin Miao, Wenyu Xu, Chen Zhang | 2019-03-19 |
| 10236346 | Transistor having a high germanium percentage fin channel and a gradient source/drain junction doping profile | Zhenxing Bi, Peng Xu, Chen Zhang | 2019-03-19 |
| 10236293 | FinFET CMOS with silicon fin N-channel FET and silicon germanium fin P-channel FET | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236290 | Method and structure for improving vertical transistor | Zhenxing Bi, Juntao Li, Peng Xu | 2019-03-19 |
| 10236289 | Approach to fabrication of an on-chip resistor with a field effect transistor | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2019-03-19 |
| 10236219 | VFET metal gate patterning for vertical transport field effect transistor | Brent A. Anderson, Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee, Junli Wang | 2019-03-19 |
| 10236214 | Vertical transistor with variable gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2019-03-19 |
| 10229996 | Strained stacked nanowire field-effect transistors (FETs) | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2019-03-12 |
| 10229987 | Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins | Zuoguang Liu, Ruilong Xie, Tenko Yamashita | 2019-03-12 |
| 10229985 | Vertical field-effect transistor with uniform bottom spacer | Juntao Li, Peng Xu, Heng Wu | 2019-03-12 |
| 10229983 | Methods and structures for forming field-effect transistors (FETs) with low-k spacers | Huiming Bu, Peng Xu | 2019-03-12 |
| 10229971 | Integration of thick and thin nanosheet transistors on a single chip | Xin Miao, Wenyu Xu, Chen Zhang | 2019-03-12 |
| 10229920 | One-time programmable vertical field-effect transistor | Qintao Zhang, Juntao Li, Geng Wang | 2019-03-12 |
| 10229919 | Vertical field effect transistor including integrated antifuse | Juntao Li, Geng Wang, Qintao Zhang | 2019-03-12 |
| 10229857 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2019-03-12 |
| 10224431 | Wrapped source/drain contacts with enhanced area | Zuoguang Liu, Heng Wu, Peng Xu | 2019-03-05 |
| 10224334 | Anti-fuse with reduced programming voltage | Juntao Li, Chengwen Pei, Geng Wang | 2019-03-05 |