Issued Patents All Time
Showing 676–700 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10685886 | Fabrication of logic devices and power devices on the same substrate | Juntao Li, Liying Jiang, John G. Gaudiello | 2020-06-16 |
| 10686014 | Semiconductor memory device having a vertical active region | Juntao Li, Takashi Ando, Dexin Kong | 2020-06-16 |
| 10686048 | Vertical fin with a gate structure having a modified gate geometry | Peng Xu | 2020-06-16 |
| 10680102 | Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2020-06-09 |
| 10680081 | Vertical transistors with improved top source/drain junctions | Muthumanickam Sankarapandian, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-06-09 |
| 10680064 | Techniques for VFET top source/drain epitaxy | Cheng Chi, Chi-Chun Liu, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2020-06-09 |
| 10680000 | Vertical field effect transistor including integrated antifuse | Juntao Li, Geng Wang, Qintao Zhang | 2020-06-09 |
| 10679998 | Vertical field effect transistor including integrated antifuse | Juntao Li, Geng Wang, Qintao Zhang | 2020-06-09 |
| 10679992 | Integrated device with vertical field-effect transistors and hybrid channels | Zhenxing Bi, Zheng Xu, Dexin Kong | 2020-06-09 |
| 10679939 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2020-06-09 |
| 10679906 | Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness | Chanro Park, Ruilong Xie, Tenko Yamashita | 2020-06-09 |
| 10679894 | Airgap spacers formed in conjunction with a late gate cut | Julien Frougier, Ruilong Xie, Chanro Park | 2020-06-09 |
| 10680063 | Method of manufacturing stacked SiGe nanotubes | Juntao Li, Choonghyun Lee | 2020-06-09 |
| 10680107 | Nanosheet transistor with stable structure | — | 2020-06-09 |
| 10672888 | Vertical transistors having improved gate length control | Xin Miao, Wenyu Xu, Chen Zhang | 2020-06-02 |
| 10672887 | Vertical FET with shaped spacer to reduce parasitic capacitance | Junli Wang, Theodorus E. Standaert, Veeraraghavan S. Basker | 2020-06-02 |
| 10672862 | High density vertically integrated FEOL MIM capacitor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-06-02 |
| 10669579 | DNA sequencing with stacked nanopores | Zhenxing Bi, Juntao Li, Xin Miao | 2020-06-02 |
| 10665783 | Nanoparticle with plural functionalities, and method of forming the nanoparticle | Qing Cao, Zhengwen Li, Fei Liu | 2020-05-26 |
| 10665714 | Vertical transistors with various gate lengths | Juntao Li, Choonghyun Lee, Shogo Mochizuki | 2020-05-26 |
| 10665698 | Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2020-05-26 |
| 10665694 | Vertical transistors having improved gate length control | Xin Miao, Wenyu Xu, Chen Zhang | 2020-05-26 |
| 10665692 | Non-self aligned gate contacts formed over the active region of a transistor | Ruilong Xie, Chanro Park, Julien Frougier | 2020-05-26 |
| 10665666 | Method of forming III-V on insulator structure on semiconductor substrate | Xin Miao, Wenyu Xu, Chen Zhang | 2020-05-26 |
| 10665512 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti, James J. Kelly +1 more | 2020-05-26 |