Issued Patents All Time
Showing 701–725 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10665511 | Self-limiting liners for increasing contact trench volume in N-type and P-type transistors | Choonghyun Lee, Juntao Li, Peng Xu | 2020-05-26 |
| 10665505 | Self-aligned gate contact isolation | Peng Xu, Ekmini Anuja De Silva, Ruilong Xie | 2020-05-26 |
| 10665414 | Piezoelectric vacuum transistor | Qing Cao, Zhengwen Li, Fei Liu | 2020-05-26 |
| 10658590 | Techniques for forming RRAM cells | Juntao Li, Dexin Kong, Takashi Ando | 2020-05-19 |
| 10658583 | Forming RRAM cell structure with filament confinement | Juntao Li, Dexin Kong, Takashi Ando | 2020-05-19 |
| 10658507 | Vertical transistor pass gate device | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-05-19 |
| 10658506 | Fin cut last method for forming a vertical FinFET device | Chanro Park | 2020-05-19 |
| 10658493 | Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates | Zhenxing Bi, Nicolas Loubet, Xin Miao, Wenyu Xu, Chen Zhang | 2020-05-19 |
| 10658481 | Self-aligned gate cut in direct stacked vertical transport field effect transistor (VTFET) | Chen Zhang, Tenko Yamashita, Xin Miao | 2020-05-19 |
| 10658473 | Gate cut device fabrication with extended height gates | Andrew M. Greene, John R. Sporre, Peng Xu | 2020-05-19 |
| 10658459 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Cheng Chi, Ruilong Xie, John H. Zhang | 2020-05-19 |
| 10658387 | Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation | Juntao Li, Zuoguang Liu, Xin Miao | 2020-05-19 |
| 10658310 | Secure semiconductor chip by piezoelectricity | Qing Cao, Fei Liu, Zhengwen Li | 2020-05-19 |
| 10658246 | Self-aligned vertical fin field effect transistor with replacement gate structure | Chen Zhang, Tenko Yamashita, Xin Miao, Juntao Li | 2020-05-19 |
| 10651378 | Resistive random-access memory | Choonghyun Lee, Juntao Li, Peng Xu | 2020-05-12 |
| 10644150 | Tunnel field-effect transistor with reduced subthreshold swing | Xin Miao, Chen Zhang, Wenyu Xu | 2020-05-05 |
| 10644138 | Fin field-effect transistors with enhanced strain and reduced parasitic capacitance | Juntao Li, Choonghyun Lee, Shogo Mochizuki | 2020-05-05 |
| 10644108 | Strained and unstrained semiconductor device features formed on the same substrate | Juntao Li, Peng Xu | 2020-05-05 |
| 10644007 | Decoupling capacitor on strain relaxation buffer layer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2020-05-05 |
| 10643996 | III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface | Jeehwan Kim | 2020-05-05 |
| 10643006 | Semiconductor chip including integrated security circuit | Oleg Gluschenkov | 2020-05-05 |
| 10636895 | Vertical transport field effect transistor on silicon with defined junctions | Chen Zhang, Xin Miao, Wenyu Xu | 2020-04-28 |
| 10636887 | Self-limiting fin spike removal | Choonghyun Lee, Juntao Li, Peng Xu | 2020-04-28 |
| 10636709 | Semiconductor fins with dielectric isolation at fin bottom | Peng Xu, Jay William Strane | 2020-04-28 |
| 10636694 | Dielectric isolation in gate-all-around devices | Robin Hsin Kuo Chao, Nicolas Loubet, Pietro Montanini, Ruilong Xie | 2020-04-28 |