Issued Patents All Time
Showing 301–325 of 437 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9929091 | Vertical fuse structures | Juntao Li, Chih-Chao Yang | 2018-03-27 |
| 9917082 | Approach to fabrication of an on-chip resistor with a field effect transistor | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-03-13 |
| 9917105 | Replacement fin process in SSOI wafer | Bruce B. Doris, Hong He, Ali Khakifirooz | 2018-03-13 |
| 9917081 | Semiconductor device including finFET and fin varactor | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-03-13 |
| 9911738 | Vertical-transport field-effect transistors with a damascene gate strap | Hiroaki Niimi, Kwan-Yong Lim, Brent A. Anderson | 2018-03-06 |
| 9911663 | Preventing buried oxide gouging during planar and FinFET processing on SOI | Kern Rim | 2018-03-06 |
| 9911657 | Semiconductor device including finFET and fin varactor | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2018-03-06 |
| 9911601 | Epitaxial silicon germanium fin formation using sacrificial silicon fin templates | Hong He, Juntao Li, Chih-Chao Yang | 2018-03-06 |
| 9905469 | Method and structure for forming FinFET CMOS with dual doped STI regions | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-02-27 |
| 9893154 | Recess liner for silicon germanium fin formation | Timothy J. McArdle, Judson R. Holt | 2018-02-13 |
| 9882048 | Gate cut on a vertical field effect transistor with a defined-width inorganic mask | Brent A. Anderson, Sivananda K. Kanakasabapathy, Jeffrey C. Shearer, Stuart A. Sieg, John R. Sporre | 2018-01-30 |
| 9881869 | Middle of the line integrated efuse in trench EPI structure | Hong He, Juntao Li, Chih-Chao Yang | 2018-01-30 |
| 9882006 | Silicon germanium fin channel formation | Hong He, Nicolas Loubet | 2018-01-30 |
| 9881926 | Static random access memory (SRAM) density scaling by using middle of line (MOL) flow | Veeraraghavan S. Basker, Kangguo Cheng, Sivananda K. Kanakasabapathy, Theodorus E. Standaert | 2018-01-30 |
| 9876009 | CMOS compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-01-23 |
| 9871116 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-01-16 |
| 9865739 | Replacement metal gate structures | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2018-01-09 |
| 9853127 | Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process | Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie | 2017-12-26 |
| 9853022 | MIM capacitor formation in RMG module | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-12-26 |
| 9847261 | Metal reflow for middle of line contacts | Juntao Li, Chih-Chao Yang | 2017-12-19 |
| 9842931 | Self-aligned shallow trench isolation and doping for vertical fin transistors | Brent A. Anderson, Fee Li Lie | 2017-12-12 |
| 9837535 | Directional deposition of protection layer | Hong He, Juntao Li, Chih-Chao Yang | 2017-12-05 |
| 9837309 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner | 2017-12-05 |
| 9818650 | Extra gate device for nanosheet | Bruce B. Doris, Terence B. Hook | 2017-11-14 |
| 9812567 | Precise control of vertical transistor gate length | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert | 2017-11-07 |