JW

Junli Wang

IBM: 418 patents #38 of 70,183Top 1%
Globalfoundries: 20 patents #152 of 4,424Top 4%
SS Stmicroelectronics Sa: 13 patents #86 of 1,676Top 6%
TE Tessera: 4 patents #104 of 271Top 40%
SO Sony: 4 patents #8,966 of 25,231Top 40%
AS Adeia Semiconductor Solutions: 2 patents #9 of 57Top 20%
EU East China Normal University: 1 patents #33 of 168Top 20%
📍 Slingerlands, NY: #1 of 96 inventorsTop 2%
🗺 New York: #26 of 115,490 inventorsTop 1%
Overall (All Time): #509 of 4,157,543Top 1%
437
Patents All Time

Issued Patents All Time

Showing 326–350 of 437 patents

Patent #TitleCo-InventorsDate
9805987 Self-aligned punch through stopper liner for bulk FinFET Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-10-31
9805935 Bottom source/drain silicidation for vertical field-effect transistor (FET) Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie 2017-10-31
9799765 Formation of a bottom source-drain for vertical field-effect transistors Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Shogo Mochizuki 2017-10-24
9793402 Retaining strain in finFET devices Bruce B. Doris, Gauri Karve, Fee Li Lie 2017-10-17
9793175 FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-10-17
9786656 Integration of bipolar transistor into complimentary metal-oxide-semiconductor process Brent A. Anderson, Xuefeng Liu 2017-10-10
9786563 Fin pitch scaling for high voltage devices and low voltage devices on the same wafer Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-10-10
9780091 Fin pitch scaling for high voltage devices and low voltage devices on the same wafer Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-10-03
9768079 Extra gate device for nanosheet Bruce B. Doris, Terence B. Hook 2017-09-19
9768118 Contact having self-aligned air gap spacers Juntao Li, Chih-Chao Yang 2017-09-19
9761699 Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures Bruce B. Doris, Hong He, Nicolas Loubet 2017-09-12
9761496 Field effect transistor contacts Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-09-12
9761500 FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-09-12
9755071 Merged gate for vertical transistors Brent A. Anderson, Fee Li Lie, Edward J. Nowak 2017-09-05
9748380 Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure Fee Li Lie, Shogo Mochizuki 2017-08-29
9741792 Bulk nanosheet with dielectric isolation Kangguo Cheng, Bruce B. Doris 2017-08-22
9741577 Metal reflow for middle of line contacts Juntao Li, Chih-Chao Yang 2017-08-22
9735246 Air-gap top spacer and self-aligned metal gate for vertical fets Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-08-15
9728642 Retaining strain in finFET devices Bruce B. Doris, Gauri Karve, Fee Li Lie 2017-08-08
9716042 Fin field-effect transistor (FinFET) with reduced parasitic capacitance Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-07-25
9716045 Directly forming SiGe fins on oxide Kangguo Cheng, Hong He, Juntao Li 2017-07-25
9704990 Vertical FET with strained channel Shogo Mochizuki 2017-07-11
9698226 Recess liner for silicon germanium fin formation Timothy J. McArdle, Judson R. Holt 2017-07-04
9698215 MIM capacitor formation in RMG module Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-07-04
9698212 Three-dimensional metal resistor formation Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert 2017-07-04